Event-Driven QDI Circuits Nabil Imam 1 , Filipp Akopyan 2 , John - - PowerPoint PPT Presentation

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Event-Driven QDI Circuits Nabil Imam 1 , Filipp Akopyan 2 , John - - PowerPoint PPT Presentation

A Digital Neurosynaptic Core Using Event-Driven QDI Circuits Nabil Imam 1 , Filipp Akopyan 2 , John Arthur 2 , Paul Merolla 2 , Rajit Manohar 1 , Dharmendra Modha 2 1 Cornell University 2 IBM Research Almaden Neuromorphic VLSI Biological nerve


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SLIDE 1

A Digital Neurosynaptic Core Using Event-Driven QDI Circuits

Nabil Imam1, Filipp Akopyan2, John Arthur2, Paul Merolla2, Rajit Manohar1, Dharmendra Modha2

1Cornell University 2IBM Research Almaden

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SLIDE 2

Neuromorphic VLSI

05/7/2012 – 2/16

  • Biological nerve cell models in silicon
  • Real-time, low-power operation
  • Commercial and medical applications
  • Tools for brain science
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SLIDE 3

Spiking Neural Networks

TIME

05/7/2012 – 3/16

  • Neuron
  • Dendrites (inputs)
  • Axon (output)
  • Synapses (connections)
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SLIDE 4

Models in Silicon

Differential Equations (e.g. Hodgkin-Huxley, Integrate-and-Fire, etc) Analog Circuits

  • Computatation
  • Intrinsic properties
  • Network connectivity
  • Efficiency
  • ~1009 neurons and ~10012 synapses in the human brain
  • 20 W Power
  • 2 L Volume

05/7/2012 – 4/16

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SLIDE 5

Computation Memory

Off-chip Memory For Synaptic Information

Implementation Challenges

05/7/2012 – 5/16

Communication

AER Packet

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SLIDE 6

Crossbar Synapses

05/7/2012 – 6/16

  • Integrated Computation

and Memory

  • Crossbar

– Rows: Axons – Columns: Dendrites – Junctions: Synapses

  • Flexibility
  • Efficiency: Large fanout

in one operation

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SLIDE 7

Scalable Neurosynaptic Core

  • Crossbar Synapses
  • Digital Circuits

– Deterministic – Scalable (45nm SOI)

  • Asynchronous design

– Minimal power dissipation when idle – Fast when active – Robust

  • Scalable to a multi-core/multi-chip system

05/7/2012 – 7/16

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SLIDE 8

System Architecture

04/11/2012 – 8/14

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SLIDE 9

Neuron Model

05/7/2012 – 9/16

฀ if Vi(t)   Spike 1 Vi(t 1)  0

฀ V(t 1) V(t)  Leak  [A j(t) W j  S j

j1 k

]

Leaky Integrate-And-Fire

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SLIDE 10

Communication Infrastructure

AER transmitter and receiver for fan-out Routing fabric for multi-core communication Scheduler for synchronization

05/7/2012 – 10/16

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SLIDE 11

Chip Test

05/7/2012 – 11/16

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SLIDE 12

Example Application:

Sound Localization

05/7/2012 – 12/16

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SLIDE 13

Example Application:

Odor Recognition

Neuron Index [C]

05/7/2012 – 13/16

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SLIDE 14

Example Applications

Pong! Motor Control Auto-associative Memory Visual Recognition

05/7/2012 – 14/16

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SLIDE 15

Conclusion

  • Neurosynaptic Core

– Digital Asynchronous Circuits – Crossbar synapses – Scalable to multiple cores and multiple chips

  • Applications

– 1-1 hardware-software correspondence – Sensory-motor activity – Bio-inspired solutions to technological problems

05/7/2012 – 15/16

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SLIDE 16

A Digital Neurosynaptic Core Using Event-Driven QDI Circuits

Nabil Imam1, Filipp Akopyan2, John Arthur2, Paul Merolla2, Rajit Manohar1, Dharmendra Modha2

1Cornell University 2IBM Research Almaden

05/7/2012 – 16/16