Equivalence Checking using Grbner Bases Amr Sayed-Ahmed 1 Daniel - - PowerPoint PPT Presentation

Equivalence Checking using Gröbner Bases

Amr Sayed-Ahmed1 Daniel Große1,2 Mathias Soeken3 Rolf Drechsler1,2

1University of Bremen, Germany 2DFKI GmbH, Germany 3EPFL, Switzerland

Email: asahmed@informatik.uni-bremen.de

FMCAD, October 2016

1

Introduction

◮ Formal verification circumvents costly bugs ◮ Automated verification of floating-point circuits at gate level is

still a major challenge

◮ The proposed algebraic technique is a fully automated

verification for floating-point circuits

2

Introduction

◮ Formal verification circumvents costly bugs ◮ Automated verification of floating-point circuits at gate level is

still a major challenge

◮ The proposed algebraic technique is a fully automated

verification for floating-point circuits

2

Introduction

◮ Formal verification circumvents costly bugs ◮ Automated verification of floating-point circuits at gate level is

still a major challenge

◮ The proposed algebraic technique is a fully automated

verification for floating-point circuits

2

Outline

Symbolic Computation Algebraic Combinational Equivalence Checking (ACEC) Reverse Engineering Arithmetic Sweeping Experimental Results Conclusion

3

Outline

Symbolic Computation Algebraic Combinational Equivalence Checking (ACEC) Reverse Engineering Arithmetic Sweeping Experimental Results Conclusion

4

Algebraic Decision Procedure

◮ Ideal Membership Testing:

Recursive Division Gröbner Bases Model G = {g1, . . . , gs} Equivalence Relationship pr Remainder Checking Equivalence Inconsistency r r = 0 r = 0

5

Modeling a Circuit as Gröbner Bases

◮ Modeling Logic Gates:

z = ¬a ⇒ g := −z + 1 − a z = a ⊕ b ⇒ g := −z + a + b − 2ab z = a ∧ b ⇒ g := −z + ab z = a ∨ b ⇒ g := −z + a + b − ab

6

Modeling a Circuit as Gröbner Bases

◮ Modeling Logic Gates:

z = ¬a ⇒ g := −z + 1 − a z = a ⊕ b ⇒ g := −z + a + b − 2ab z = a ∧ b ⇒ g := −z + ab z = a ∨ b ⇒ g := −z + a + b − ab

◮ Full Adder Example:

a g6 g2 b g5 s c g3 g4 g1 cout

x1 x4 x3 x2

leading monomial tail terms ց ւ g1 := −cout −x4x3 + x4 + x3

6

Modeling a Circuit as Gröbner Bases

◮ Modeling Logic Gates:

z = ¬a ⇒ g := −z + 1 − a z = a ⊕ b ⇒ g := −z + a + b − 2ab z = a ∧ b ⇒ g := −z + ab z = a ∨ b ⇒ g := −z + a + b − ab

◮ Full Adder Example:

a g6 g2 b g5 s c g3 g4 g1 cout

x1 x4 x3 x2

leading monomial tail terms ց ւ g1 := −cout −x4x3 + x4 + x3 g2 := −s − 2x1c + x1 + c

6

Modeling a Circuit as Gröbner Bases

◮ Modeling Logic Gates:

z = ¬a ⇒ g := −z + 1 − a z = a ⊕ b ⇒ g := −z + a + b − 2ab z = a ∧ b ⇒ g := −z + ab z = a ∨ b ⇒ g := −z + a + b − ab

◮ Full Adder Example:

a g6 g2 b g5 s c g3 g4 g1 cout

x1 x4 x3 x2

leading monomial tail terms ց ւ g1 := −cout −x4x3 + x4 + x3 g2 := −s − 2x1c + x1 + c g3 := −x4 + x2c g4 := −x3 + ab g5 := −x2 − ab + a + b g6 := −x1 − 2ab + a + b

6

Modeling a Circuit as Gröbner Bases

◮ Modeling Logic Gates:

z = ¬a ⇒ g := −z + 1 − a z = a ⊕ b ⇒ g := −z + a + b − 2ab z = a ∧ b ⇒ g := −z + ab z = a ∨ b ⇒ g := −z + a + b − ab

◮ Full Adder Example:

leading monomial tail terms ց ւ g1 := −cout −x4x3 + x4 + x3 g2 := −s − 2x1c + x1 + c g3 := −x4 + x2c g4 := −x3 + ab g5 := −x2 − ab + a + b g6 := −x1 − 2ab + a + b

◮ Leading monomials are relatively prime =

⇒ The model is Gröbner bases

6

Ideal Membership Testing

◮ Following Full Adder Example: specification polynomial

pr := −2ccout − s + c + b + a

◮ Its model

g1 := −cout −x4x3 + x4 + x3 g2 := −s − 2x1c + x1 + c g3 := −x4 + x2c g4 := −x3 + ab g5 := −x2 − ab + a + b g6 := −x1 − 2ab + a + b

◮ Recursive Division:

7

Ideal Membership Testing

◮ Following Full Adder Example: specification polynomial

pr := −2ccout − s + c + b + a

◮ Its model

g1 := −cout −x4x3 + x4 + x3 g2 := −s − 2x1c + x1 + c g3 := −x4 + x2c g4 := −x3 + ab g5 := −x2 − ab + a + b g6 := −x1 − 2ab + a + b

◮ Recursive Division:

pr := −2ccout − s + c + b + a

g1

− − − → −s +2x4x3 − 2x4 − 2x3 + c + b + a

g2

− − − →

7

Ideal Membership Testing

◮ Following Full Adder Example: specification polynomial

pr := −2ccout − s + c + b + a

◮ Its model

g1 := −cout −x4x3 + x4 + x3 g2 := −s − 2x1c + x1 + c g3 := −x4 + x2c g4 := −x3 + ab g5 := −x2 − ab + a + b g6 := −x1 − 2ab + a + b

◮ Recursive Division:

g2

− − − → 2x4x3 − 2x4 − 2x3 + 2x1c − x1 + b + a

g3

− − − →

7

Ideal Membership Testing

◮ Following Full Adder Example: specification polynomial

pr := −2ccout − s + c + b + a

◮ Its model

g1 := −cout −x4x3 + x4 + x3 g2 := −s − 2x1c + x1 + c g3 := −x4 + x2c g4 := −x3 + ab g5 := −x2 − ab + a + b g6 := −x1 − 2ab + a + b

◮ Recursive Division:

g3

− − − → 2x3x2c − 2x3 − 2x2c + 2x1c − x1 + b + a

g4

− − − →

7

Ideal Membership Testing

◮ Following Full Adder Example: specification polynomial

pr := −2ccout − s + c + b + a

◮ Its model

g1 := −cout −x4x3 + x4 + x3 g2 := −s − 2x1c + x1 + c g3 := −x4 + x2c g4 := −x3 + ab g5 := −x2 − ab + a + b g6 := −x1 − 2ab + a + b

◮ Recursive Division:

g4

− − − → 2x2cba − 2x2c + 2x1c − x1 − 2ba + b + a

g5

− − − → 2x1c − x1 + 4cba − 2ca − 2cb − 2ab + b + a

g6

− − − → 0

7

Outline

Symbolic Computation Algebraic Combinational Equivalence Checking (ACEC) Reverse Engineering Arithmetic Sweeping Experimental Results Conclusion

8

Flow of ACEC

Circuit Netlist 1 Gröbner Modeling N1 Gröbner Modeling Circuit Netlist 2 N2 Combined Model G1 G2 G

9

Flow of ACEC

Circuit Netlist 1 Gröbner Modeling N1 Gröbner Modeling Circuit Netlist 2 N2 Combined Model G1 G2 Membership Testing Output Relationships Inconsistency Equivalence G

9

Flow of ACEC

Circuit Netlist 1 Gröbner Modeling N1 Gröbner Modeling Circuit Netlist 2 N2 Combined Model G1 G2 Membership Testing Output Relationships Inconsistency Equivalence G

= ⇒ Computationally Infeasible

9

Flow of ACEC

Circuit Netlist 1 Gröbner Modeling N1 Gröbner Modeling Circuit Netlist 2 N2 Combined Model G1 G2 Reverse Engineering G G′ wG Model Rewriting G Identifying & Abstracting Arithmetic Units G′ wG G′ G′: Rewritten Combined Model wG: Abstracted Polynomials Set of Arithmetic Units

9

Flow of ACEC

Reverse Engineering Arithmetic Sweeping G′ wG G sG Deducing Relationships G′ wG Membership Testing Internal Relationships G′ wG Model Simplification Equivelance/ Inconsistency sG G′

9

Flow of ACEC

Reverse Engineering Arithmetic Sweeping G′ wG G Membership Testing Output Relationships sG Inconsistency Equivalence

9

Outline

Symbolic Computation Algebraic Combinational Equivalence Checking (ACEC) Reverse Engineering Arithmetic Sweeping Experimental Results Conclusion

10

Reverse Engineering

◮ Based on detecting carry bits propagation within arithmetic units

(integer adders and multipliers)

◮ Full adder model revealing carry terms:

g1 : −s + c + b + a + 4cba − 2cb − 2ca − 2ba g2 : −cout − 2cba + cb + ca + ba

◮ Identifying subsets of polynomials that share carry terms,

therefore, model arithmetic components

◮ Model rewriting is required for:

◮ Revealing carry terms ◮ Removing vanishing monomials (redundant monomials that

always evaluate to zero)

◮ Abstraction by Gaussian elimination, for the full adder:

2g2 + g1 → gr : −2cout − s + c + b + a

11

Reverse Engineering

◮ Based on detecting carry bits propagation within arithmetic units

(integer adders and multipliers)

◮ Full adder model revealing carry terms:

g1 : −s + c + b + a + 4cba − 2cb − 2ca − 2ba g2 : −cout − 2cba + cb + ca + ba

◮ Identifying subsets of polynomials that share carry terms,

therefore, model arithmetic components

◮ Model rewriting is required for:

◮ Revealing carry terms ◮ Removing vanishing monomials (redundant monomials that

always evaluate to zero)

◮ Abstraction by Gaussian elimination, for the full adder:

2g2 + g1 → gr : −2cout − s + c + b + a

11

Reverse Engineering

◮ Based on detecting carry bits propagation within arithmetic units

(integer adders and multipliers)

◮ Full adder model revealing carry terms:

g1 : −s + c + b + a + 4cba − 2cb − 2ca − 2ba g2 : −cout − 2cba + cb + ca + ba

◮ Identifying subsets of polynomials that share carry terms,

therefore, model arithmetic components

◮ Model rewriting is required for:

◮ Revealing carry terms ◮ Removing vanishing monomials (redundant monomials that

always evaluate to zero)

◮ Abstraction by Gaussian elimination, for the full adder:

2g2 + g1 → gr : −2cout − s + c + b + a

11

Reverse Engineering

◮ Based on detecting carry bits propagation within arithmetic units

(integer adders and multipliers)

◮ Full adder model revealing carry terms:

g1 : −s + c + b + a + 4cba − 2cb − 2ca − 2ba g2 : −cout − 2cba + cb + ca + ba

◮ Identifying subsets of polynomials that share carry terms,

therefore, model arithmetic components

◮ Model rewriting is required for:

◮ Revealing carry terms ◮ Removing vanishing monomials (redundant monomials that

always evaluate to zero)

◮ Abstraction by Gaussian elimination, for the full adder:

2g2 + g1 → gr : −2cout − s + c + b + a

11

Reverse Engineering

◮ Based on detecting carry bits propagation within arithmetic units

(integer adders and multipliers)

◮ Full adder model revealing carry terms:

g1 : −s + c + b + a + 4cba − 2cb − 2ca − 2ba g2 : −cout − 2cba + cb + ca + ba

◮ Identifying subsets of polynomials that share carry terms,

therefore, model arithmetic components

◮ Model rewriting is required for:

◮ Revealing carry terms ◮ Removing vanishing monomials (redundant monomials that

always evaluate to zero)

◮ Abstraction by Gaussian elimination, for the full adder:

2g2 + g1 → gr : −2cout − s + c + b + a

11

Reverse Engineering

◮ Based on detecting carry bits propagation within arithmetic units

(integer adders and multipliers)

◮ Full adder model revealing carry terms:

g1 : −s + c + b + a + 4cba − 2cb − 2ca − 2ba g2 : −cout − 2cba + cb + ca + ba

◮ Identifying subsets of polynomials that share carry terms,

therefore, model arithmetic components

◮ Model rewriting is required for:

◮ Revealing carry terms ◮ Removing vanishing monomials (redundant monomials that

always evaluate to zero)

◮ Abstraction by Gaussian elimination, for the full adder:

2g2 + g1 → gr : −2cout − s + c + b + a

11

Reverse Engineering

◮ Based on detecting carry bits propagation within arithmetic units

(integer adders and multipliers)

◮ Full adder model revealing carry terms:

g1 : −s + c + b + a + 4cba − 2cb − 2ca − 2ba g2 : −cout − 2cba + cb + ca + ba

◮ Identifying subsets of polynomials that share carry terms,

therefore, model arithmetic components

◮ Model rewriting is required for:

◮ Revealing carry terms ◮ Removing vanishing monomials (redundant monomials that

always evaluate to zero)

◮ Abstraction by Gaussian elimination, for the full adder:

2g2 + g1 → gr : −2cout − s + c + b + a

11

Reverse Engineering: 1) Model Rewriting

◮ XOR rewriting preserves inputs and outputs of chains of XOR

gates

◮ Parallel Adder Model:

c2 = D2 ∨ (X2 ∧ D1) ∨ (X2 ∧ X1 ∧ D0) = ⇒ g1 := −c2 + X2X1a2b2a1b1a0b0 − X2X1a1b1a0b0 − X2X1a2b2a0b0 − X2a2b2a1b1 + X2X1a0b0 + X2a1b1 + a2b2 s2 = X2 ⊕ c1 = ⇒ g2 := −s2 − 2c1X2 + c1 + X2 c1 = D1 ∨ (X1 ∧ D0)= ⇒ g3 := −c1−X1a1b1a0b0 + X1a0b0 + a1b1 s1 = X1 ⊕ c0 = ⇒ g4 := −s1 − 2c0X1 + c0 + X1 c0 = D0 = ⇒ g5 := −c0 + a0b0 s0 = X0 = ⇒ g6 := −s0 + X0 Xi = ai ⊕ bi = ⇒ gk−i−1 := −Xi − 2aibi + bi + ai Di = ai ∧ bi = ⇒ gk−i := −Di + aibi

12

Reverse Engineering: 1)Model Rewriting

◮ Common rewriting preserves shared variables between

polynomials

◮ Parallel adder model after XOR rewriting:

g1 := −c2 + X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2 − 2c1X2 + c1 + X2 g3 := −c1 + X1a0b0 + a1b1 g4 := −s1 − 2c0X1 + c0 + X1 g5 := −c0 + a0b0 g6 := −s0 + X0 g7 := −X0 − 2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ X0, c0 and c1 will be eliminated

13

Reverse Engineering: 1)Model Rewriting

◮ Common rewriting preserves shared variables between

polynomials

◮ Parallel adder model after XOR rewriting:

g1 := −c2 + X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2 − 2c1X2 + c1 + X2 g3 := −c1 + X1a0b0 + a1b1 g4 := −s1 − 2c0X1 + c0 + X1 g5 := −c0 + a0b0 g6 := −s0 + X0 g7 := −X0 − 2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ X0, c0 and c1 will be eliminated

13

Reverse Engineering: 1)Model Rewriting

◮ Common rewriting preserves shared variables between

polynomials

◮ Parallel adder model after XOR rewriting:

g1 := −c2 + X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2 − 2c1X2 + c1 + X2 g3 := −c1 + X1a0b0 + a1b1 g4 := −s1 − 2c0X1 + c0 + X1 g5 := −c0 + a0b0 g6 := −s0 + X0 g7 := −X0 − 2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ X0, c0 and c1 will be eliminated

13

Reverse Engineering: 2) Extracting Arithmetic Units

◮ Parallel adder model after common rewriting:

g1 := −c2+X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2−2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1 g4 := −s1−2X1a0b0 + a0b0 + X1 g6 := −s0 + −2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ Abstraction by Gaussian elimination:

14

Reverse Engineering: 2) Extracting Arithmetic Units

◮ Parallel adder model after common rewriting:

g1 := −c2+X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2−2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1 g4 := −s1−2X1a0b0 + a0b0 + X1 g6 := −s0 + −2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ Abstraction by Gaussian elimination:

14

Reverse Engineering: 2) Extracting Arithmetic Units

◮ Parallel adder model after common rewriting:

g1 := −c2+X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2−2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1 g4 := −s1−2X1a0b0 + a0b0 + X1 g6 := −s0 + −2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ Abstraction by Gaussian elimination:

2g1 + g2 − → gres := −2c2 +2X2X1a0b0 + 2X2a1b1 + 2a2b2 − s2 −2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1

14

Reverse Engineering: 2) Extracting Arithmetic Units

◮ Parallel adder model after common rewriting:

g1 := −c2+X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2−2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1 g4 := −s1−2X1a0b0 + a0b0 + X1 g6 := −s0 + −2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ Abstraction by Gaussian elimination:

2g1 + g2 − → gres := −2c2 ✭✭✭✭✭✭✭✭✭✭ ✭ ❤❤❤❤❤❤❤❤❤❤ ❤ +2X2X1a0b0 + 2X2a1b1 + 2a2b2 − s2 ✭✭✭✭✭✭✭✭✭✭ ✭ ❤❤❤❤❤❤❤❤❤❤ ❤ −2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1

14

Reverse Engineering: 2) Extracting Arithmetic Units

◮ Parallel adder model after common rewriting:

g1 := −c2+X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2−2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1 g4 := −s1−2X1a0b0 + a0b0 + X1 g6 := −s0 + −2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ Abstraction by Gaussian elimination:

gres := −2c2 − s2 + X2 + X1a0b0+2a2b2+a1b1 2gres+g4 − → gres := −4c2−2s2−s1+2X2+X1+4a2b2+2a1b1+a0b0

14

Reverse Engineering: 2) Extracting Arithmetic Units

◮ Parallel adder model after common rewriting:

g1 := −c2+X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2−2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1 g4 := −s1−2X1a0b0 + a0b0 + X1 g6 := −s0 + −2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ Abstraction by Gaussian elimination:

gres := −4c2 − 2s2 − s1 + 2X2 + X1+4a2b2+2a1b1+a0b0 2gres + g6 − → gres := −8c2 − 4s2 − 2s1 − s0 + 4X2 + 2X1+8a2b2+4a1b1 + b0 + a0

14

Reverse Engineering: 2) Extracting Arithmetic Units

◮ Parallel adder model after common rewriting:

g1 := −c2+X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2−2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1 g4 := −s1−2X1a0b0 + a0b0 + X1 g6 := −s0 + −2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ Abstraction by Gaussian elimination:

gres := −8c2 − 4s2 − 2s1 − s0 + 4X2 + 2X1+8a2b2+4a1b1 + b0 + a0 gres + 2g8 − → gres := −8c2 − 4s2 − 2s1 − s0 + 4X2+8a2b2 + 2b1 + 2a1 + b0 + a0

14

Reverse Engineering: 2) Extracting Arithmetic Units

◮ Parallel adder model after common rewriting:

g1 := −c2+X2X1a0b0 + X2a1b1 + a2b2 g2 := −s2−2X2X1a0b0 − 2X2a1b1 + X2 + X1a0b0+a1b1 g4 := −s1−2X1a0b0 + a0b0 + X1 g6 := −s0 + −2a0b0 + b0 + a0 g8 := −X1 − 2a1b1 + b1 + a1 g9 := −X2 − 2a2b2 + b2 + a2

◮ Abstraction by Gaussian elimination:

gres := −8c2 − 4s2 − 2s1 − s0 + 4X2+8a2b2 + 2b1 + 2a1 + b0 + a0 gres + 4g9 − → gres := −8c2 − 4s2 − 2s1 − s0 + 4b2 + 4a2 + 2b1 + 2a1 + b0 + a0

14

Outline

Symbolic Computation Algebraic Combinational Equivalence Checking (ACEC) Reverse Engineering Arithmetic Sweeping Experimental Results Conclusion

15

Arithmetic Sweeping

Reverse Engineering Arithmetic Sweeping G′ wG G sG Deducing Relationships G′ wG Membership Testing Internal Relationships G′ wG Model Simplification Equivelance/ Inconsistency sG G′

16

Deducing Relationships

DPU2 DPU1 DPU3 DPU4

C1 Netlist C2 Netlist

Transitive Fan-in Transitive Fan-in

◮ Partitioning the combined model based on the extracted

arithmetic information

17

Deducing and Testing Relationships

DPU2 DPU1

−x + ˆ x

G′

− − − →+ r

Transitive Fan-in Transitive Fan-in

◮ Deducing and testing bit relationships between variables of the

transitive fan-in of arithmetic units

18

Deducing and Testing Relationships

DPU2 DPU1

−2n−1sn−1 − · · · − s0+2n−1ˆ sn−1 + · · · + ˆ s0

wG

− − − − →+ r

◮ Testing the word relationship between output variables of

compared arithmetic units, using the abstracted polynomials

18

Model Simplification

DPU3 DPU4

C1 Netlist C2 Netlist

◮ Merging proved equivalent variables simplifies the combined

model dramatically

◮ Therefore, testing output relationships wrt. the simplified model

is computationally feasible

19

Model Simplification

DPU3 DPU4

C1 Netlist C2 Netlist

◮ Merging proved equivalent variables simplifies the combined

model dramatically

◮ Therefore, testing output relationships wrt. the simplified model

is computationally feasible

19

Outline

Symbolic Computation Algebraic Combinational Equivalence Checking (ACEC) Reverse Engineering Arithmetic Sweeping Experimental Results Conclusion

20

Experimental Results

Simple Multiplier Complex Multiplier EXP Adder EXP Adder Normalize & Round Optimized- Normalize & Round

Left Hand Side Right Hand Side ea eb ea eb fa fb fa fb fp ep ˆ fp ˆ ep

Figure: Compared FP Multiplier Circuits

21

Experimental Results

Multiplier FP operand Commercial ABC ACEC Architecture # bits (h:m:s) (h:m:s) (h:m:s) SP-CT-BK 16 00:08:50 TO 00:01:42 SP-WT-CH 16 00:09:08 TO 00:01:44 SP-CT-BK 24 TO TO 00:17:49 SP-WT-CH 24 TO TO 00:25:58 SP-CT-BK 32 TO TO 02:24:01 SP-WT-CH 32 TO TO 03:41:43 SP → Simple Partial Product WT → Wallace Tree CT → Compressor Tree CH → Carry Look Ahead Adder BK → Brent-Kung Adder TO=100 Hour

22

Outline

Symbolic Computation Algebraic Combinational Equivalence Checking (ACEC) Reverse Engineering Arithmetic Sweeping Experimental Results Conclusion

23

Conclusion

◮ New algebraic equivalence checking technique for circuits that

combine data-path and control logic

◮ New reverse engineering algorithm to extract and abstract

arithmetic components

◮ Arithmetic sweeping based on input and output boundaries of the

abstracted components

◮ Efficient polynomial representation (negative-Davio

decomposition)

◮ Checking equivalence of large floating-point multipliers which

cannot be verified by state-of-art equivalence checkers

◮ Verifying heavy optimized circuits and dealing with

non-equivalent circuits are still major challenges

24

Conclusion

◮ New algebraic equivalence checking technique for circuits that

combine data-path and control logic

◮ New reverse engineering algorithm to extract and abstract

arithmetic components

◮ Arithmetic sweeping based on input and output boundaries of the

abstracted components

◮ Efficient polynomial representation (negative-Davio

decomposition)

◮ Checking equivalence of large floating-point multipliers which

cannot be verified by state-of-art equivalence checkers

◮ Verifying heavy optimized circuits and dealing with

non-equivalent circuits are still major challenges

24

Conclusion

◮ New algebraic equivalence checking technique for circuits that

combine data-path and control logic

◮ New reverse engineering algorithm to extract and abstract

arithmetic components

◮ Arithmetic sweeping based on input and output boundaries of the

abstracted components

◮ Efficient polynomial representation (negative-Davio

decomposition)

◮ Checking equivalence of large floating-point multipliers which

cannot be verified by state-of-art equivalence checkers

◮ Verifying heavy optimized circuits and dealing with

non-equivalent circuits are still major challenges

24

Conclusion

◮ New algebraic equivalence checking technique for circuits that

combine data-path and control logic

◮ New reverse engineering algorithm to extract and abstract

arithmetic components

◮ Arithmetic sweeping based on input and output boundaries of the

abstracted components

◮ Efficient polynomial representation (negative-Davio

decomposition)

◮ Checking equivalence of large floating-point multipliers which

cannot be verified by state-of-art equivalence checkers

◮ Verifying heavy optimized circuits and dealing with

non-equivalent circuits are still major challenges

24

Conclusion

◮ New algebraic equivalence checking technique for circuits that

combine data-path and control logic

◮ New reverse engineering algorithm to extract and abstract

arithmetic components

◮ Arithmetic sweeping based on input and output boundaries of the

abstracted components

◮ Efficient polynomial representation (negative-Davio

decomposition)

◮ Checking equivalence of large floating-point multipliers which

cannot be verified by state-of-art equivalence checkers

◮ Verifying heavy optimized circuits and dealing with

non-equivalent circuits are still major challenges

24

Conclusion

◮ New algebraic equivalence checking technique for circuits that

combine data-path and control logic

◮ New reverse engineering algorithm to extract and abstract

arithmetic components

◮ Arithmetic sweeping based on input and output boundaries of the

abstracted components

◮ Efficient polynomial representation (negative-Davio

decomposition)

◮ Checking equivalence of large floating-point multipliers which

cannot be verified by state-of-art equivalence checkers

◮ Verifying heavy optimized circuits and dealing with

non-equivalent circuits are still major challenges

24

Equivalence Checking using Gröbner Bases

Amr Sayed-Ahmed1 Daniel Große1,2 Mathias Soeken3 Rolf Drechsler1,2

1University of Bremen, Germany 2DFKI GmbH, Germany 3EPFL, Switzerland

Email: asahmed@informatik.uni-bremen.de

FMCAD, October 2016

25