Embedded RTOS Programming Class Project m-moore september 19, 2013 - - PDF document

embedded rtos programming class project m moore september
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Embedded RTOS Programming Class Project m-moore september 19, 2013 - - PDF document

Embedded RTOS Programming Class Project m-moore september 19, 2013 Features GUI-based Monitor/Control of Toy CPU All CPU Registers Readable/Writable Main-Memory Port-Access Program Single-Step Program Lock-Step Run


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SLIDE 1

Embedded RTOS Programming Class Project m-moore – september 19, 2013

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SLIDE 2

Features

  • GUI-based Monitor/Control of Toy CPU
  • All CPU Registers Readable/Writable
  • Main-Memory Port-Access
  • Program Single-Step
  • Program Lock-Step Run
  • Load Main Memory From File
  • Dump Main Memory To File
  • Automatic Test

RTOS-Related

  • Four Threads of Varying Priority
  • Mail-Queue Communication Between Threads
  • Meta-Watchdog Thread (other threads report-in)
  • Selectable error() vs mbed_reset() on error detection
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SLIDE 3

void watchdogThread(void const *args) // overall watchdog.

{ int dHeartbeat; // heartbeat counter. Watchdog_RTOS watchdog; // the one and only watchdog. dHeartbeat = 0; // initialize. watchdog.kick(WATCHDOG_S); // initialize watchdog. while (1) // thread loop. { // all other threads report-in. // blocking wait on all of them. queueWatchdogThread_0.get(osWaitForever); queueWatchdogThread_1.get(osWaitForever); queueWatchdogThread_2.get(osWaitForever); watchdog.kick(); // reset watchdog timer. dHeartbeat++; // thread heartbeat. if (!(dHeartbeat % HB_MODULO)) led3 = !led3; Thread::wait(THREAD_3_WAIT); // multitasking. } // thread loop. }

Meta-watchdog thread. All other threads check-in via queue. This thread is also its own watchdog.

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SLIDE 4

Tk GUI PySerial /dev/ttyACM* Python code USBSerial USB CPU Data Pins mmSPI Host Data CPU Pins SPI MBED Host PC FPGA

DESIGN DIAGRAM

USB SPI

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SLIDE 5

Accumulator MMdataL MMdataH MMadr Program Counter Instruction Register R0 R1 R2 R3 Shadow Registers SPI-out SPI-in Instruction Decoder MainMemory R0 Port1RW Port1Adr Port0Adr Port0R Control Lines 16-bits x 256 addresses

instruction_override

CPU Implementation Diagram

[15:13] [12:10] [7:0] [9] [8] Immediate DEST WE SRC PCE Instruction Word Fields CPU-clk SPI-clk

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SLIDE 6

ShiftReg SPI,CPU clocks SPI vector mmSPI commands Mail queue tFromHost altera tToHost bufferOut To LCD Main thread SPI thread diagnosticThread ProcessIncomingSerial SPI vector Mail queue ProcessOutgoingSerial mmSPI SPIprocessingThread

Mbed Firmware Implementation Diagram

Other Threads Report- In watchdogThread

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SLIDE 7

Testing

  • 3. python speed testing – needed 40mS delay.
  • 4. automated test using 'prog_add_list'

Result – no errors detected over a 17-hour run. ============================ Wed Sep 18 07:43:26 PDT 2013 test iteration 2049 compare dump_test.txt against dump_add_list.txt ============================ Wed Sep 18 07:43:56 PDT 2013 test iteration 2050 compare dump_test.txt against dump_add_list.txt

  • 1. debug with LCD & signalTap
  • 2. manual GUI exercise.

419,468,950 SPI clocks. 6,057,750 CPU clocks. 17-hour 26-minute test run. 2050 iterations. no errors.