efficient persist barriers for multicores
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MICRO-48 Efficient Persist Barriers for Multicores Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, Stratis Viglas Summary Efficient persist barrier Used to implement persistency models Persistency = when stores become durable


  1. MICRO-48 Efficient Persist Barriers for Multicores Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, Stratis Viglas

  2. Summary • Efficient persist barrier • Used to implement persistency models • Persistency = when stores become durable (Consistency = when stores become visible) • Evaluated • Buffered Epoch Persistency • Bulk Strict Persistency December 9, 2015 MICRO-48 2

  3. Persistent Memory Access Granularity Access Latency December 9, 2015 MICRO-48 3

  4. Persistent Memory Access Granularity Secondary Storage DRAM Cache Access Latency December 9, 2015 MICRO-48 3

  5. Persistent Memory Access Granularity PCM 3D Xpoint Secondary Storage STT-MRAM DRAM NVRAM Cache Access Latency December 9, 2015 MICRO-48 3

  6. Persistent Memory Access Granularity PCM 3D Xpoint Secondary Storage STT-MRAM DRAM NVRAM Cache Access Latency Fast, fine grained persistence. December 9, 2015 MICRO-48 3

  7. Persistent Memory Advantages : Unify memory and storage Access to persistent data through processor load/store interface Challenge : Maintaining consistency of data structures in memory December 9, 2015 MICRO-48 4

  8. Consistency Challenge Core Cache DRAM Software Controlled Secondary Storage December 9, 2015 MICRO-48 5

  9. Consistency Challenge Core Core Cache Cache Hardware Controlled DRAM NVRAM Software Controlled Secondary Storage Secondary Storage December 9, 2015 MICRO-48 5

  10. Linked List - Naïve Cache HEAD Pseudo-code Node Node 1. Create Node 0 1 2. Update Node Pointer 3. Update Head Pointer HEAD Node Node 0 1 NVRAM December 9, 2015 MICRO-48 6

  11. Linked List - Naïve Cache HEAD Pseudo-code Node Node Node 1. Create Node 0 1 2 2. Update Node Pointer 3. Update Head Pointer HEAD Node Node 0 1 NVRAM December 9, 2015 MICRO-48 6

  12. Linked List - Naïve Cache HEAD Pseudo-code Node Node Node 1. Create Node 0 1 2 2. Update Node Pointer 3. Update Head Pointer HEAD Node Node Node 0 1 2 NVRAM December 9, 2015 MICRO-48 6

  13. Linked List - Naïve Cache HEAD Pseudo-code Node Node Node 1. Create Node 0 1 2 2. Update Node Pointer 3. Update Head Pointer HEAD Node Node Node 0 1 2 NVRAM December 9, 2015 MICRO-48 6

  14. Linked List - Naïve Cache Pseudo-code 1. Create Node System Crash! 2. Update Node Pointer 3. Update Head Pointer HEAD Node Node Node 0 1 2 NVRAM December 9, 2015 MICRO-48 6

  15. Linked List - Failsafe Cache Pseudo-code HEAD 1. Create Node Node Node 0 1 2. Update Node Pointer 3. Persist Barrier HEAD 4. Update Head Pointer Node Node 0 1 NVRAM December 9, 2015 MICRO-48 7

  16. Linked List - Failsafe Cache Pseudo-code HEAD 1. Create Node Node Node Node 0 1 2 2. Update Node Pointer 3. Persist Barrier HEAD 4. Update Head Pointer Node Node 0 1 NVRAM December 9, 2015 MICRO-48 7

  17. Linked List - Failsafe Cache Pseudo-code HEAD 1. Create Node Node Node Node 0 1 2 2. Update Node Pointer 3. Persist Barrier HEAD 4. Update Head Pointer Node Node Node 0 1 2 NVRAM December 9, 2015 MICRO-48 7

  18. Linked List - Failsafe Cache Pseudo-code HEAD 1. Create Node Node Node Node 0 1 2 2. Update Node Pointer 3. Persist Barrier HEAD 4. Update Head Pointer Node Node Node 0 1 2 NVRAM December 9, 2015 MICRO-48 7

  19. Linked List - Failsafe Cache Pseudo-code HEAD 1. Create Node Node Node Node 0 1 2 2. Update Node Pointer 3. Persist Barrier HEAD 4. Update Head Pointer Node Node Node 0 1 2 NVRAM December 9, 2015 MICRO-48 7

  20. Linked List - Failsafe Pseudo-code 1. Create Node Epoch A 2. Update Node Pointer 3. Persist Barrier 4. Update Head Pointer Epoch B December 9, 2015 MICRO-48 8

  21. Linked List - Failsafe Pseudo-code 1. Create Node 2. Update Node Pointer Programmer 3. Persist Barrier Introduced 4. Update Head Pointer December 9, 2015 MICRO-48 8

  22. Linked List - Failsafe Pseudo-code 1. Create Node 2. Update Node Pointer Programmer 3. Persist Barrier Introduced 4. Update Head Pointer Divide program execution into epochs through programmer inserted persist barriers = Epoch Persistence December 9, 2015 MICRO-48 8

  23. Epoch Persistence* St a St b St c St a Epoch 1 Epoch 2 Epoch 3 Persist Barrier a b c a d e d p q d Visibility St d St e b a c d e Persistence St d Persist Barrier St p St q St d … * Pelley et. al., “Memory Persistency”, in ISCA-2014. December 9, 2015 MICRO-48 9

  24. Epoch Persistence* St a St b St c St a Epoch 1 Epoch 2 Epoch 3 Persist Barrier a b c a d e d p q d Visibility St d St e b a c d e Persistence St d Persist Barrier St p St q St d … * Pelley et. al., “Memory Persistency”, in ISCA-2014. December 9, 2015 MICRO-48 9

  25. Epoch Persistence* St a St b St c St a Epoch 1 Epoch 2 Epoch 3 Persist Barrier a b c a d e d p q d Visibility St d St e b a c d e Persistence St d Persist Barrier St p St q St d … * Pelley et. al., “Memory Persistency”, in ISCA-2014. December 9, 2015 MICRO-48 9

  26. Epoch Persistence* St a St b St c St a Epoch 1 Epoch 2 Epoch 3 Persist Barrier a b c a d e d p q d Visibility St d St e b a c d e Persistence St d Persist Barrier St p St q St d … * Pelley et. al., “Memory Persistency”, in ISCA-2014. December 9, 2015 MICRO-48 9

  27. Epoch Persistence* St a St b St c St a Epoch 1 Epoch 2 Epoch 3 Persist Barrier a b c a d e d p q d Visibility St d St e b a c d e Persistence St d Persist Barrier St p St q St d … * Pelley et. al., “Memory Persistency”, in ISCA-2014. December 9, 2015 MICRO-48 9

  28. Epoch Persistence* St a St b St c St a Epoch 1 Epoch 2 Epoch 3 Persist Barrier a b c a d e d p q d Visibility St d St e b a c d e Persistence St d Persist Barrier St p St q St d … * Pelley et. al., “Memory Persistency”, in ISCA-2014. December 9, 2015 MICRO-48 9

  29. Epoch Persistence* St a St b St c St a Epoch 1 Epoch 2 Epoch 3 Persist Barrier a b c a d e d p q d Visibility St d St e b a c d e Persistence St d Persist Barrier St p St q St d … Persist operations happen in the critical path of execution. * Pelley et. al., “Memory Persistency”, in ISCA-2014. December 9, 2015 MICRO-48 9

  30. Buffered Epoch Persistence* through Lazy Barrier (LB) • Implementation of Epoch Persistence • Durability lags visibility • To allow performing persist operations out of critical path * Pelley et. al., “Memory Persistency”, in ISCA-2014. * Condit et. al., “Better I/O through byte-addressable, persistent memory”, in SOSP-2009. December 9, 2015 MICRO-48 10

  31. Buffered Epoch Persistence* through Lazy Barrier (LB) Epoch 1 Epoch 2 Epoch 3 Visibility a b c a d e d p q d − Conflicting request a b c d e Persistence * Pelley et. al., “Memory Persistency”, in ISCA-2014. * Condit et. al., “Better I/O through byte-addressable, persistent memory”, in SOSP-2009. December 9, 2015 MICRO-48 11

  32. Buffered Epoch Persistence* through Lazy Barrier (LB) Epoch 1 Epoch 2 Epoch 3 Visibility a b c a d e d p q d − Conflicting request a b c d e Persistence * Pelley et. al., “Memory Persistency”, in ISCA-2014. * Condit et. al., “Better I/O through byte-addressable, persistent memory”, in SOSP-2009. December 9, 2015 MICRO-48 11

  33. Buffered Epoch Persistence* through Lazy Barrier (LB) Epoch 1 Epoch 2 Epoch 3 Visibility a b c a d e d p q d − Conflicting request a b c d e Persistence * Pelley et. al., “Memory Persistency”, in ISCA-2014. * Condit et. al., “Better I/O through byte-addressable, persistent memory”, in SOSP-2009. December 9, 2015 MICRO-48 11

  34. Buffered Epoch Persistence* through Lazy Barrier (LB) Epoch 1 Epoch 2 Epoch 3 Visibility a b c a d e d p q d − Conflicting request a b c d e Persistence Cache Line Eviction * Pelley et. al., “Memory Persistency”, in ISCA-2014. * Condit et. al., “Better I/O through byte-addressable, persistent memory”, in SOSP-2009. December 9, 2015 MICRO-48 11

  35. Buffered Epoch Persistence* through Lazy Barrier (LB) Epoch 1 Epoch 2 Epoch 3 Visibility a b c a d e d p q d − Conflicting request a b c d e Persistence * Pelley et. al., “Memory Persistency”, in ISCA-2014. * Condit et. al., “Better I/O through byte-addressable, persistent memory”, in SOSP-2009. December 9, 2015 MICRO-48 11

  36. Buffered Epoch Persistence* through Lazy Barrier (LB) Epoch 1 Epoch 2 Epoch 3 Visibility a b c a d e d p q d − Conflicting request a b c d e Persistence * Pelley et. al., “Memory Persistency”, in ISCA-2014. Conflicts bring persist operations back in the critical path. * Condit et. al., “Better I/O through byte-addressable, persistent memory”, in SOSP-2009. December 9, 2015 MICRO-48 11

  37. Intra-thread Conflict Epoch 1 Epoch 2 Epoch 3 Visibility a b c a d e d p q d − Conflicting request a b c d e Persistence December 9, 2015 MICRO-48 12

  38. Intra-thread Conflict Epoch 1 Epoch 2 Epoch 3 Visibility a b c a d e d p q d − Conflicting request a b c d e Persistence December 9, 2015 MICRO-48 12

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