SLIDE 1
Outline
- 1. aiT’s pipeline analysis
- 3. Why improve its efficiency?
- 5. BDD based pipeline analysis
- 7. Generating pipeline analyzers
- 9. Status and prospects
Efficient Analysis of Pipeline Models for WCET Computation Stephan - - PowerPoint PPT Presentation
Efficient Analysis of Pipeline Models for WCET Computation Stephan - - PowerPoint PPT Presentation
A b s I n t Efficient Analysis of Pipeline Models for WCET Computation Stephan Wilhelm (sw@absint.com) AbsInt GmbH and Saarland University Outline 1. aiTs pipeline analysis 3. Why improve its efficiency? 5. BDD based pipeline analysis 7.
SLIDE 2
SLIDE 3
The aiT-Framework
Executable Program Control-Flow Reconstruction Value Analyzer Worst-Case Execution Path Analysis WCET Visualization Pipeline Analyzer Cache Analyzer
SLIDE 4
Cache Analysis
Pipeline Analysis
Pipeline Abstraction
b
c e a d
Pipeline Model CFG
instruction A instruction B
a
b
c d e a d e
Timing Anomalies!
State explosion.
SLIDE 5
Timing Anomalies
- local worst case vs. global worst case
– cache hit on global worst-case path (Lundquist/Stenström) – “unintuitive behavior” – no upper bound
- Caused by features like: caches, out-of-order execution,
branch prediction, ... No local worst-case decisions. State explosion.
SLIDE 6
Symbolic Representation of FSM State Sets
a = 1 b = 1 a = 0 b = 0 a = 1 b = 0 a = 0 b = 1
A 2-bit automaton
- BDD size depends on variable ordering
- worst case: exponential
- in most cases better orderings are possible
01 00 01 11 10 00 01
FSM state sets 1 characteristic functions
¬a∧b ¬a
BDD’s
a b 1 a 1 1
SLIDE 7
BDD based Pipeline Analysis
00 01 10
00: 01 01: 10 10: 01
11
A 2-bit automaton The program
10 00 01 11
- 1. Partition the set
10 00 10 00 01 11
- 2. Compute images
10 10 00 01
- 3. Apply inputs
10 00 01
- 4. Compute union
01 11 10 00
Start set
SLIDE 8
Model Specification & Validation
- Documentation is often incorrect/incomplete.
- Model specification is error-prone.
- Trace validation is difficult.
Generate analysis from HDL specification.
- Verilog and VHDL can be compiled into FSM’s
(Cheng, 1994).
– Implemented in VIS model checker.
SLIDE 9
Generating Pipeline Analyzers
HDL Pipeline Analyzer Program (CFG) Simplified HDL FSM specification Model Checker Properties Abstraction HDL->FSM compiler
SLIDE 10
Status and Prospects
1. Implementation of proof-of-concept.
– For simple examples. – Only one basic block.
2. Integration with DFA framework (PAG). 3. Integration with CFG representation. 4. Specification of a real pipeline.
– Infineon Tricore 2
5. Compare against “classic aiT”.
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