EECS 678: Introduction to Operating Systems
Heechul Yun
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EECS 678: Introduction to Operating Systems Heechul Yun 1 About - - PowerPoint PPT Presentation
EECS 678: Introduction to Operating Systems Heechul Yun 1 About Me Heechul Yun, Assistant Prof., Dept. of EECS Office: 3040 Eaton, 236 Nichols Email: heechul.yun@ku.edu Research Areas Operating systems and architecture
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– Office: 3040 Eaton, 236 Nichols – Email: heechul.yun@ku.edu
– Operating systems and architecture support for embedded/real- time systems
– Worked as a systems software engineer at Samsung Electronics
– http://ittc.ku.edu/~heechul
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– MWF 8:00 – 8:50 @ LEAP2 G415 – Office hour: MF: 11 - 11:50 a.m. @ 3040 Eaton – Discuss OS concepts and the design of major OS components
– Occasional online quizzes to check your understanding
– Hands-on system programming experiences. – Each lab includes lab discussion and an assignment
– Design and implement some parts of OS. – 3 projects: 1) Shell, 2) CPU scheduler, 3) Memory allocator (2week/prj) – To do in groups of two persons. Solo project is also allowed.
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Applications Operating System Computer Hardware
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– How to organize the OS?
– How to exchange data among different programs?
– How to maximize/guarantee performance and fairness?
– How to name/access resources ?
– How to protect with each other?
– How to prevent unauthorized access?
– How to prevent system crash?
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20 http://www.catb.org/esr/writings/taouu/html/ch02s01.html
IBM 029 card punch
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Applications Operating System Computer Hardware
A von Neumann architecture
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H Sutter, “The Free Lunch Is Over”, Dr. Dobb's Journal, 2009
Registers
Cache
Memory
Core Processor
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Registers
Cache
Memory
Core
Registers
Cache Core Processor
Shared Cache
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Memory
Register s
Cache Core
Register s
Cache Core Processor
Shared Cache Register s
Cache Core
Register s
Cache Core Processor
Shared Cache
Memory
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Performance of various levels of storage depends on
distance from the CPU, size, and process technology used
Movement between levels of storage hierarchy can be
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save CPU states (registers) execute the associated interrupt service routine (ISR) restore the CPU states return to the interrupted program
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Process A Process B Process C Physical Memory
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Virtual address Physical address
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Thread 1: Deposiit(acc, 10) LOAD R1, account->balance ADD R1, amount STORE R1, account->balance Thread 2: : Deposiit(acc, 10) LOAD R1, account->balance ADD R1, amount STORE R1, account->balance Deposit(account, amount) { { account->balance += amount; }
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Reliable and secure Insecure and unreliable networks File system Mechanical disk Infinite capacity Limited RAM capacity Multiple computers A single computer Abstraction Reality
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