[PPT] - ece BRADLEY DEPARTMENT of ELECTRICAL & COMPUTER ENGINEERING PowerPoint Presentation

SLIDE 1

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Vladimir S. Podosinov

SLIDE 2

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Motivation for the project
Other devices on the market
Transceiver structure and design
Testing Results
Conclusions and Future Work
Questions

SLIDE 3

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

5 10 15 20 25 30 35 40 45 50

40
35
30
25
20
15
10
5

Frequency (Hz) Fs = 100 Power (dB)

Suppose there are 3 different information channels that need to be received at the same time

Different bandwidths
Different modulations

SLIDE 4

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Instead of wideband antenna, a narrowband antenna with

tunable frequency can be used, and hop between frequencies quickly

Need to see if performance drops due to frequency
hopping. Need bit error rate (BER) testing platform

Transmitter Receiver f1 f2 f3 f1 f2 f3

SLIDE 5

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
A good way to test system is to use

software defined radio (SDR)

Can implement any modulation
Can modify platform at any time

SLIDE 6

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Software defined radio is independent of the components,

adding a new capability, becomes writing a new firmware, not building a new device.

Software Defined Radio in the Ideal Case

SLIDE 7

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Current SDRs on the Market

SLIDE 8

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
There are multiple devices that can be used for Software

defined radio on the market

Ettus Research has 2 platforms, and recently introduced a new
ne

USRP USRP2

SLIDE 9

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
There is also a Rice University

WARP (Wireless Open-Access Research Platform)

And there is a commercial product

from Lyrtech

ComBlock also has some modules

that implement a modem and are developing SDR platform

SLIDE 10

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Rice University WARP platform is pretty expensive,

and so are products from Lyrtech

Ettus Research is a bargain, and there is a large

community supporting it with GnuRadio

ComBlock modules are pre-programmed. Each new

feature will require a different block. Or IP (intellectual property) needs to be purchased

SLIDE 11

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Transceiver Structure

SLIDE 12

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

SLIDE 13

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

SLIDE 14

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Transmitter consist of DSP board, a DAC

board, and an up-converter modulator

Modulator range: 950-1450 MHz
DAC: Max sampling rate 125 MSPS;

maximum output bandwidth 13 MHz

DSP and DAC are connected together

using IDE cable through an external memory interface

External interface memory clock is used for the DAC transfers
At the moment clock rate is 12 MHz

SLIDE 15

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Receiver consists of down-

converter demodulator with the ADCs

FPGA for preprocessing

and communication control with the DSP

Down-converter range:

900-1575 MHz

ADC sample rate: 40

MSPS

SLIDE 16

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

AGC

10 10 10

AGC DAC CLK AGC DAC ADC CLK I Q

CIC

10 10 10 10

Matched Filter

10 10

MOD TYPE

FPGA TO DSP TRANSFER MODULE

RESET

10 10

SYSTEM CLK

20

DATA HINT HRDY STROBE IF FREQUENCY SOURCE

DELAY ADJUST CLOCK GENERATOR

10 MHz clock 1 MHz clock

TED

10 10 10 10

ERROR DELAY ERROR MAX

FPGA: Xilinx Spartan-3 400

SLIDE 17

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
DSP Code
Network Communication
Baseband Signal Generation
Signal reception and correction
Error Calculation

SLIDE 18

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
FPGA Code
DC Offset Correction
Automatic Gain Control (AGC)
IF Down conversion and Decimation
Matched Filtering
Timing Correction
DSP Communication

SLIDE 19

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

START Data <= 2 INTACK Data => 4 WADDR Data => Addr1/Addr2 WDATA Data => Samples CPUWAIT Data => 2 Data <= DSP_IN EXIT Data => 4 HINT = 0 / HRW = 0 CTRL = 00 HINT = 1 / HRW = 0 CTRL = 10 HRDY = 0 / HRW = 0 CTRL = 01 DATA_CNT = 255 / HRW = 0 CTRL = 01 HINT = 0 / HRW = 0 CTRL = 00 HINT = 1 / HRW = 1 CTRL = 11 HINT = 1 / HRW = 1 CTRL = 11 HINT = 0 / HRW = 0 CTRL = 10 HRDY = 1 / HRW = 1 CTRL = 10 DATA_CNT < 255 / HRW = 0 CTRL = 01 HINT = 1, HRW =0 / HRW = 1 CTRL = 00 HINT = 1, HRW = 1, DATA[1] = 1 / HRW = 1 CTRL = 00 HINT = 1, HRW = 1, DATA[1] = 0 / HRW = 0 CTRL = 10 HINT = 0 / HRW = 0 CTRL = 00

SLIDE 20

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Linear Feedback Shift Register (LFSR)
LFSRs are used to generate maximal length

sequences (m-sequence)

SLIDE 21

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
BIOS is the real-time operating

system (RTOS) used in some of the TI’s DSPs

Advantages of the BIOS over

traditional coding is the use of scheduler

SLIDE 22

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

SLIDE 23

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

ISR() { Interrupt triggered code } main() { while(1) { Functions(); Other code; } }

ISR() { Call SWI(); } main() { Call setup functions; return; } SWI() { Process interrupt here; } OtherThread() { Perform other code; }

Code without BIOS Code with BIOS

SLIDE 24

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Test Results

SLIDE 25

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Ref 5 dBm Att 0 dB * 1 SA AVG A Center 1.45 GHz Span 5 MHz 500 kHz/ 3DB RBW 100 kHz VBW 300 kHz SWT 2.5 ms

90
80
70
60
50
40
30
20
10

SWP 64 of 64 1 Marker 1 [T1 ]

24.95 dBm

1.449959936 GHz 2 Delta 2 [T1 ]

26.45 dB
1.008012821 MHz

3 Delta 3 [T1 ]

26.00 dB

1.009615385 MHz Ref 5 dBm Att 0 dB * 1 SA AVG A Center 1.45 GHz Span 5 MHz 500 kHz/ 3DB RBW 100 kHz VBW 300 kHz SWT 2.5 ms

90
80
70
60
50
40
30
20
10

SWP 64 of 64 1 Marker 1 [T1 ]

16.21 dBm

1.450456731 GHz 2 Marker 2 [T1 ]

16.90 dBm

1.449447115 GHz 3 Marker 3 [T1 ]

55.33 dBm

1.451418269 GHz 4 Marker 4 [T1 ]

55.95 dBm

1.448493590 GHz

SLIDE 26

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Ref 5 dBm Att 0 dB * 1 SA AVG A Center 1.45 GHz Span 5 MHz 500 kHz/ 3DB RBW 100 kHz VBW 300 kHz SWT 2.5 ms

90
80
70
60
50
40
30
20
10

SWP 64 of 64 1 Marker 1 [T1 ]

13.32 dBm

1.449959936 GHz 2 Delta 2 [T1 ]

42.36 dB
1.008012821 MHz

3 Delta 3 [T1 ]

40.00 dB

1.009615385 MHz Ref 5 dBm Att 0 dB * 1 SA AVG A Center 1.45 GHz Span 5 MHz 500 kHz/ 3DB RBW 100 kHz VBW 300 kHz SWT 2.5 ms

90
80
70
60
50
40
30
20
10

SWP 64 of 64 1 Marker 1 [T1 ]

22.77 dBm

1.451458333 GHz 2 Delta 2 [T1 ]

0.15 dB
1.995192308 MHz

3 Delta 3 [T1 ]

2.82 dB
969.551282051 kHz

4 Delta 4 [T1 ]

3.45 dB
3.012820513 MHz

SLIDE 27

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

QPSK 16-QAM

SLIDE 28

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

8-PAM 16-APSK

SLIDE 29

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

3 4 5 6 7 8 9 10 10

6

10

5

10

4

10

3

10

2

10

1

Eb/N0 (dB) Bit Error Rate BPSK/QPSK Theory BPSK Measured QPSK Measured BASK Theory BASK Measured

SLIDE 30

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

5 6 7 8 9 10 11 12 10

5

10

4

10

3

10

2

10

1

Eb/N0 (dB) Bit Error Rate 8-PSK Theory 8-PSK Measured 16-QAM Theory 16-QAM Measured 16-APSK Theory 16-APSK Measured

SLIDE 31

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

3 4 5 6 7 8 9 10 10

2

10

1

Eb/N0 (dB) Bit Error Rate 4-ASK Theory 4-ASK Measured 8-PAM Theory 8-PAM Measured

SLIDE 32

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

SLIDE 33

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

SLIDE 34

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Modulation Error Test 1 Error Test 2 BASK 0.01643164 0.0122165 BPSK 0.0152784 0.01331759 QPSK 0.0072194 0.0188586 4-ASK 0.014609 0.014479 8-PAM 0.032588 0.032715 8-PSK 0.047863 0.0271668 16-QAM 0.0323732 0.024467 16-APSK 0.0248244 0.025308

SLIDE 35

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Modulation Error Test 1 Error Test 2 BASK 0.0165107 0.0164654 BPSK 0.0138805 0.0130997 QPSK 0.021261 0.0235587 4-ASK 0.023284 0.020410 8-PAM 0.0367070 0.03299138 8-PSK 0.030490 0.0347004 16-QAM 0.0252258 0.02521068 16-APSK 0.027396438 0.02745781

SLIDE 36

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING

Conclusions and Future Work

SLIDE 37

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Without timing error, performance of the

receiver is very good. Phase ambiguity still should be solved somehow

Under real conditions there is a 1% - 4%

error, which means for reliable link there should be an error coding, but BER will need relative measurements

SLIDE 38

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Optimizing system for one particular task and modulation
Peripherals such as audio ADC and DAC can be used to

create a full cell phone prototype and test different codecs

Ethernet can be used to create wired to wireless link
Based on the industry experience clock crystals on the

receiver need to be replaced for quality communication system

SLIDE 39

ece

BRADLEY DEPARTMENT

f ELECTRICAL & COMPUTER ENGINEERING
Use of the TI BIOS system rather then Linux
A working interface between HPI and an FPGA
An affordable platform with lots of peripherals

and a lot of possible customization

An educational tool