Does Cache Sharing on Modern CMP Matter to the Performance of - - PowerPoint PPT Presentation

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Does Cache Sharing on Modern CMP Matter to the Performance of - - PowerPoint PPT Presentation

Feb 04, 2023 461 likes •912 views

Does Cache Sharing on Modern CMP Matter to the Performance of Contemporary Multithreaded Programs? Eddy Zheng Zhang Yunlian Jiang Xipeng Shen (presenter) Computer Science Department The College of William and Mary, VA, USA Cache Sharing

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Does Cache Sharing on Modern CMP Matter to the Performance of Contemporary Multithreaded Programs?

Eddy Zheng Zhang Yunlian Jiang Xipeng Shen (presenter) Computer Science Department The College of William and Mary, VA, USA

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The College of William and Mary

Cache Sharing

  • A common feature on modern CMP

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Cache Sharing on CMP

  • A double-edged sword
  • Reduces communication latency
  • But causes conflicts & contention

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The College of William and Mary

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Cache Sharing on CMP

  • A double-edged sword
  • Reduces communication latency
  • But causes conflicts & contention

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Non-Uniformity

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Many Efforts for Exploitation

  • Example: shared-cache-aware scheduling
  • Assigning suitable programs/threads to the same

chip

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  • Independent jobs
  • Job Co-Scheduling [Snavely+:00, Snavely+:02, El-

Moursy+:06, Fedorova+:07, Jiang+:08, Zhou+:09]

  • Parallel threads of server applications
  • Thread Clustering [Tam+:07]
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Overview of this Work (1/3)

  • A surprising finding
  • Insignificant effects from shared cache on a recent

multithreaded benchmark suite (PARSEC)

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  • Drawn from a systematic measurement
  • thousands of runs
  • 7 dimensions on levels of programs, OS, &

architecture

  • derived from timing results
  • confirmed by hardware performance counters
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Overview of this Work (2/3)

  • A detailed analysis
  • Reason
  • three mismatches between executables and CMP

cache architecture

  • Cause
  • the current development and compilation are
  • blivious to cache sharing

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Overview of this Work (3/3)

  • An exploration of the implications
  • Exploiting cache sharing deserves not less but

more attention.

  • But to exert the power, cache-sharing-aware

transformations are critical

  • Cuts half of cache misses
  • Improves performance by 36%.

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Outline

  • Experiment design
  • Measurement and findings
  • Cache-sharing-aware transformation
  • Related work, summary, and conclusion.

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Benchmarks (1/3)

  • PARSEC suite by Princeton Univ [Bienia+:08]

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“focuses on emerging workloads and was designed to be representative of next-generation shared-memory programs for chip-multiprocessors”

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Benchmarks (2/3)

  • Composed of
  • RMS applications
  • Systems applications
  • ……
  • A wide spectrum of
  • working sets, locality, data sharing, synch., off-chip

traffic, etc.

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Program Description Parallelism Working Set Blackscholes Black-Scholes equation data 2MB Bodytrack body tracking data 8MB Canneal

  • sim. Annealing

unstruct. 256MB Facesim face simulation data 256MB Fluidanimate fluid dynamics data 64MB Streamcluster

  • nline clustering

data 16MB Swaptions portfolio pricing data 0.5MB X264 video encoding pipeline 16MB Dedup stream compression pipeline 256MB Ferret image search pipeline 64MB

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Benchmarks (3/3)

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Factors Covered in Measurements

Dimension Variations tions Description benchmarks 10 from PARSEC parallelism 3 data, pipeline, unstructured inputs 4 simsmall, simmedium, simlarge, native # of threads 4 1,2,4,8 assignment 3 threads assignment to cores binding 2 yes, no subset of cores 7 The cores a program uses platforms 2 Intel Xeon & AMD Operon

Program level OS level

  • Arch. level

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Intel (Xeon 5310)

32K 32K 32K 32K 8GB DRAM 32K 32K 32K 32K 4MB L2 4MB L2 4MB L2 4MB L2

Machines

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64K 64K 64K 64K 512K 512K 512K 512K 2MB L3 4GB DRAM 64K 64K 64K 64K 512K 512K 512K 512K 2MB L3 4GB DRAM

AMD (Opeteron 2352)

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Measurement Schemes

  • Running times
  • Built-in hooks in PARSEC
  • Hardware performance counters
  • PAPI
  • cache miss, mem. bus, shared data accesses

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Outline

  • Experiment design
  • Measurement and findings
  • Cache-sharing-aware transformation
  • Related work, summary, and conclusions

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Observation I: Sharing vs. Non-sharing

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Sharing vs. Non-sharing

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T1 T2

VS.

T1 T2

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Sharing vs. Non-sharing

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T1 T2

VS.

T1 T3 T3 T4 T2 T4

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Sharing vs. Non-sharing

  • Performance Evaluation (Intel)

0.2 0.4 0.6 0.8 1 1.2 1.4

2t simlarge 2t native 4t simlarge 4t native

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blackscholes bodytrack canneal facesim fluidanimate streamcluster swaptions x264

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Sharing vs. Non-sharing

  • Performance Evaluation (AMD)

0.2 0.4 0.6 0.8 1 1.2 1.4

2t simlarge 2t native 4t simlarge 4t native

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blackscholes bodytrack canneal facesim fluidanimate streamcluster swaptions x264

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Sharing vs. Non-sharing

  • L2-cache accesses & misses (Intel)

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Reasons (1/2)

1) Small amount of inter-thread data sharing

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1.75 3.5 5.25 7

blackscholes bodytrack canneal facesim fluidanimate streamcluster swaptions x264

sharing ratio of reads (%) (Intel)

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Reasons (2/2)

2) Large working sets

Program Description Parallelism Working Set Blackscholes Black-Scholes equation data 2MB Bodytrack body tracking data 8MB Canneal

  • sim. Annealing

unstruct. 256MB Facesim face simulation data 256MB Fluidanimate fluid dynamics data 64MB Streamcluster

  • nline clustering

data 16MB Swaptions portfolio pricing data 0.5MB X264 video encoding pipeline 16MB Dedup stream compression pipeline 256MB Ferret image search pipeline 64MB

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Observation II: Different Sharing Cases

  • Threads may differ
  • Different data to be processed or tasks to be

conducted.

  • Non-uniform communication and data sharing.
  • Different thread placement may give different

performance in the sharing case.

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Difgerent Sharing Cases

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T1 T2 T3 T4 T1 T3 T2 T4 T1 T4 T2 T3

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2 4 6 8 10 12 14 16

  • Max. Perf. Diff (%)

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statistically insignificant---large fluctuations across runs of the same config.

2t simlarge 2t native 4t simlarge 4t native

blackscholes bodytrack canneal facesim fluidanimate streamcluster swaptions x264

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Two Possible Reasons

  • Similar interactions among threads
  • Differences are smoothed by phase shifts

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Temporal Traces of L2 misses

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Temporal Traces of L2 misses

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Two Possible Reasons

  • Similar interactions among threads
  • Differences are smoothed by phase shifts

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Pipeline Programs

  • Two such programs: ferret, and dedup
  • Numerous concurrent stages
  • Interactions within and between stages
  • Large differences between different thread-core

assignments

  • Mainly due to load balance rather than differences in

cache sharing.

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A Short Summary

  • Insignificant influence on performance
  • Large working sets
  • Little data sharing
  • Thread placement does not matter
  • Due to uniform relations among threads
  • Hold across inputs, # threads, architecture, phases.

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Outline

  • Experiment design
  • Measurement and findings
  • Cache-sharing-aware transformation
  • Related work, summary, and conclusions

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Principle

  • Increase data sharing among siblings
  • Decrease data sharing otherwise

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Non-uniform threads Non-uniform cache sharing

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Example: streamcluster

  • riginal code

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for i = 1 to N, step =1 … … for j= T2+1 to T3 dist=foo(p[j],p[c[i]]) end … … end for i = 1 to N, step =1 … … for j= T1 to T2 dist=foo(p[j],p[c[i]]) end … … end

thread 1 thread 2

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Example: streamcluster

  • ptimized code

for i = 1 to N, step =2 … … for j= T1 to T3 dist=foo(p[j],p[c[i+1]]) end … … end for i = 1 to N, step =2 … … for j= T1 to T3 dist=foo(p[j],p[c[i]]) end … … end

thread 1 thread 2

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Performance Improvement (streamcluster)

0.25 0.5 0.75 1 4t 8t

L2 Cache Miss Mem Bus Trans

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Other Programs

Normalized L2 Misses (on Intel)

0.25 0.5 0.75 1 4t 8t 4t 8t

Blacksholes Bodytrack

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Implication

  • To exert the potential of shared cache, program-level

transformations are critical.

  • Limited existing explorations
  • Sarkar & Tullsen’08, Kumar& Tullsen’02,

Nokolopoulos’03.

* A contrast to the large body of work in OS and architecture.

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Related Work

  • Co-runs of independent programs
  • Snavely+:00, Snavely+:02, El-Moursy+:06, Fedorova+:07, Jiang+:08, Zhou

+:09, Tian+:09

  • Co-runs of parallel threads of multithreaded programs
  • Liao+:05, Tuck+:03, Tam+:07
  • Have been focused on certain aspects of CMP
  • Simulators-based for cache design
  • Old benchmarks (e.g. SPLASH-2)
  • Specific class of apps (e.g., server apps)
  • Old CMP with no shared cache

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First systematic examin. of the influence of cache sharing in modern CMP on the perf. of contemporary multithreaded apps.

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Measurement

Insignificant influence from cache

sharing despite inputs, arch, # threads, thread placement,

parallelism, phases, etc.

Analysis

Mismatch between SW & HW causing the

  • bservations.

Transformation

Large potential of cache-share-aware code

  • ptimizations.

Summary

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Conclusion

  • Yes. But the main effects show up only after

cache-sharing-aware transformations.

Does cache sharing on CMP matter to contemporary multithreaded programs?

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Thanks!

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Questions?