doe big idea concept
play

DOE Big Idea concept Chief Engineer proposed by DOE Labs Advanced - PowerPoint PPT Presentation

Dev Shenoy DOE Big Idea concept Chief Engineer proposed by DOE Labs Advanced Manufacturing Office www.manufacturing.energy.gov March 06, 2017 NICE Workshop at IBM Research-Almaden 1 | Energy Efficiency and Renewable Energy


  1. Dev Shenoy DOE “Big Idea” concept Chief Engineer proposed by DOE Labs Advanced Manufacturing Office www.manufacturing.energy.gov March 06, 2017 NICE Workshop at IBM Research-Almaden 1 | Energy Efficiency and Renewable Energy eere.energy.gov

  2. IT challenge for future electricity supply Do Nothing Energy ~ 100Pj/op 10000 New Moore scaling 8000 In 20 yrs Energy = 20fj/op TWHr IT=30-40% growth 6000 Projection based on consumer electronics 4000 + data centers New Moore scaling in 10 yrs 2000 Energy = 20fj/op IT=hold to 8% 0 2000 2005 2010 2015 2020 2025 2030 Year www.alliancetrustinvestments.com/sri-hub/posts/Energy-efficient-data-centres www.iea.org/publications/freepublications/publication/gigawatts2009.pdf

  3. Bey eyond M nd Moore Co-des design F n Framework 10,000x improvement: 20 fJ per instruction equivalent Experimental Modeling Algorithms and Software Environments Algorithms & SW Environments Application Performance Modeling • Computer System Architecture Modeling • Next generation of Structural Simulation Toolkit • Heterogeneous systems HPC models On Chip Universal Memory: • Stacked ReRAM Component Fabrication • Petabit cm -2 Densities Microarchitecture Models • Replaces DRAM & flash Hardware & Circuit On Chip Memristor Accelerator: • <1 pJ per write/read • Vector or matrix operations Processors, ASICs On Chip Photonics • • fJs per operation • Chip to chip communication • McPAT, CACTI, NVSIM, gem5 • <1 pJ per bit transfer Architectures • Photonics To next node • Memory Silicon High Performance Logic: • TFET, NcgFET x 2 ... w 1,1 w 1,2 w 2,x x 2 Circuit/IP Block Design and Modeling Test Circuit Fab and Measurement ... w 2,1 w 2,2 w 2,x x 2 ... w 3,1 w 3,2 w 3,x x 2 • SPICE/Xyce model • Subcircuit measurement w 4,1 w 4,2 w 4,x ... Compact Device Models Device Measurements Computation Devices Comm., Memory & • Single device electrical models • Single device electrical behavior • Variability and corner models • Parametric variability Device Physics Modeling Device Structure Integration and • Device physics modeling (TCAD) - - - - - Demonstration - - + + + + + + + + + • Electron transport, ion transport V TE + + + + + + + + + - Novel device structure - - • - - - Magnetic properties • Ta TaO x Pt demonstration Process Module Modeling Process Module Demonstrations • Diffusion, etch, implant • EUV and novel lithography Simulation • • Diffusion, etch, implant simulation Materials • EUV and novel lithography models Atomistic and Ab-Initio Modeling Fundamental Materials Science Example activities • DFT – VASP, Socorro • Understanding Properties/Defects via • MD – LAMMPS within a MCF Electron, Photon, & Scanning Probes • Novel Materials Synthesis

  4. Industry-Academia-Government Partnership Microelectronics: 1) Beyond von-Neumann architectures 2) Clear industry value proposition 3) Strong Partnerships 4) Ability to address critical challenges 5) A balanced portfolio of projects Open Consortium—new members able to join 4

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend


More recommend