Distributed Synthesis for Well Connected Architectures Paul Gastin, - - PowerPoint PPT Presentation

Distributed Synthesis for Well Connected Architectures

Paul Gastin, Nathalie Sznajder and Marc Zeitoun March 13th 2006 ACI Cortos Persee Versydis

Synthesis of a reactive system

inputs from E

• utputs to E

Open system S Specification ϕ

Synthesis of a reactive system

inputs from E

• utputs to E

Open system S Specification ϕ Program P

Two problems

Decide whether there exists a program st. P||E | = ϕ, ∀E. Synthesis: If so, compute such a program. For reasonable systems and specifications, the problems are decidable.

Distributed synthesis

input of E

• utput to E

Open distributed system S S1 S2 S3 S4 Specification ϕ

Distributed synthesis

input of E

• utput to E

Open distributed system S S1 S2 S3 S4 Specification ϕ P1 P2 P3 P4

Two problems

Decide the existence of a distributed program such that their joint behavior P1||P2||P3||P4||E satisfies ϕ, for all E. Synthesis : If it exists, compute such a distributed program.

Distributed synthesis

input of E

• utput to E

Open distributed system S S1 S2 S3 S4 Specification ϕ P1 P2 P3 P4

Two problems

Decide the existence of a distributed program such that their joint behavior P1||P2||P3||P4||E satisfies ϕ, for all E. Synthesis : If it exists, compute such a distributed program.

Peterson-Reif 1979, Pnueli-Rosner 1990

In general, the problem is undecidable.

The model

Example

x0 x1 x2 x3 x4 x5 a1 a2 a3 a4

The model

Example

x0 x1 x2 x3 x4 x5 a1 a2 a3 a4 Synchronous behavior

The model

Example

x0 x1 x2 x3 x4 x5 a1 a2 a3 a4 Synchronous behavior Strategies with local memory

The model

Example

x0 x1 x2 x3 x4 x5 a1 a2 a3 a4 Synchronous behavior Strategies with local memory 0-delay semantics

The model

Example

x0 x1 x2 x3 x4 x5 a1 a2 a3 a4 Synchronous behavior Strategies with local memory 0-delay semantics Input-output specifications

Undecidable architecture (Pnueli–Rosner ’90)

x0 y0 x1 y1 P0 P1

Undecidable architecture (Pnueli–Rosner ’90)

x0 y0 x1 y1 P0 P1 S

Undecidable architecture (Pnueli–Rosner ’90)

x0 y0 x1 y1 P0 P1 S $Ci$

T

$C ′

i $

Undecidable architecture (Pnueli–Rosner ’90)

x0 y0 x1 y1 P0 P1 S $Ci$

T

$C ′

i $

$Ci+1$ ⇒ T $C ′

i+1$

Decidable architecture

x0 y0 x1 y1 t P0 P1

Pipe-line decidable for global specifications (Kupferman–Vardi ’01)

Oenv P1 P2 . . . Pn On O1 O2 On−1

Pipe-line decidable for global specifications (Kupferman–Vardi ’01)

Oenv P1 P2 . . . Pn On O1 O2 On−1

Pipe-line decidable for global specifications (Kupferman–Vardi ’01)

Oenv P1 P2 . . . Pn On O1 O2 On−1

Information fork criterion (Finkbeiner–Schewe ’05)

x0 x1 p0 p1 t0 t1 p y

Information fork criterion (Finkbeiner–Schewe ’05)

x0 x1 p0 p1 t0 t1 p y x0 x1 p0 p1 t0 t1

Outline

1

Uncomparable information

2

Uniformly well connected architectures

3

Well connected architectures

Outline

1

Uncomparable information

2

Uniformly well connected architectures

3

Well connected architectures

Uncomparable information yields undecidability

Definition

For an output variable v, View(v) is the set of input variables u such that v is accessible from u.

Definition

An architecture has uncomparable information if there exist x,y output variables such that View(x) \ View(y) = ∅ and View(y) \ View(x) = ∅. Otherwise it is said to have preordered information. x0 x1 y0 y1

Uncomparable information yields undecidability

Theorem

Architectures with uncomparable information are undecidable for LTL or CTL input-output specifications.

Proof

LTL specifications : x0 x1 y0 y1 x0 x1 y0 y1

Uncomparable information yields undecidability

Theorem

Architectures with uncomparable information are undecidable for LTL or CTL input-output specifications.

Proof

LTL specifications : x0 x1 y0 y1 x0 x1 y0 y1

Uncomparable information yields undecidability

Theorem

Architectures with uncomparable information are undecidable for LTL or CTL input-output specifications.

Proof

LTL specifications : x0 x1 y0 y1 x0 x1 y0 y1 0 0 0 0 0

Outline

1

Uncomparable information

2

Uniformly well connected architectures

3

Well connected architectures

Uniformly well connected architectures

Definition

An architecture is uniformly well connected if there is a uniform way to route variables in View(v) to v for each output variable v. u v w p p s t p p p x y z

Uniformly well connected architectures

Definition

An architecture is uniformly well connected if there is a uniform way to route variables in View(v) to v for each output variable v. u v w p p s t p p p x y z u ⊕ v v ⊕ w

Network Information Flow

M M M M s s s a b c d e f g

demands M, M, M, M demands M, M

Network Information Flow : Multicast

M M M M s a b c d e f g

demands M, M, M, M demands M, M, M, M

Relations between the two problems

Theorem

The multicast reduces to checking uniform well connectedness.

Relations between the two problems

Theorem

The multicast reduces to checking uniform well connectedness.

Proof.

M M

s a b c d e f

Relations between the two problems

Theorem

The multicast reduces to checking uniform well connectedness.

Proof.

M M

s a b c d e f

M M

s a b c d e f u v w x y z s t r y y y

Relations between the two problems

Theorem

Checking uniform well connectedness reduces to the network information flow.

Relations between the two problems

Theorem

Checking uniform well connectedness reduces to the network information flow.

Proof.

s

Relations between the two problems

Theorem

Checking uniform well connectedness reduces to the network information flow.

Proof.

s s

demands s demands s

Relations between the two problems

Theorem

Checking uniform well connectedness reduces to the network information flow.

Proof.

s s

demands s demands s

Relations between the two problems

Theorem

Checking uniform well connectedness reduces to the network information flow.

Proof.

s s

demands s demands s

Complexity

Rasala Lehman-Lehman 2004

Multicast whith alphabet size q = pk (where p is prime) is NP-hard.

Complexity

Rasala Lehman-Lehman 2004

Multicast whith alphabet size q = pk (where p is prime) is NP-hard.

Theorem

Checking whether a given architecture is uniformly well connected is NP-complete.

Complexity

Rasala Lehman-Lehman 2004

Multicast whith alphabet size q = pk (where p is prime) is NP-hard.

Theorem

Checking whether a given architecture is uniformly well connected is NP-complete.

Proof.

It is trivially NP. Reduction from multicast gives NP-hardness.

Decidability criterion for uniformly well connected architectures

Theorem

Architectures with preordered information are decidable for CTL* specifications.

Decidability criterion for uniformly well connected architectures

Theorem

Architectures with preordered information are decidable for CTL* specifications.

Proof.

x1 y1 x2 y2 x3 y3 x4 y4

Decidability criterion for uniformly well connected architectures

Theorem

Architectures with preordered information are decidable for CTL* specifications.

Proof.

x1 y1 x2 y2 x3 y3 x4 y4

Decidability criterion for uniformly well connected architectures

Theorem

Architectures with preordered information are decidable for CTL* specifications.

Proof.

x1 y1 x2 y2 x3 y3 x4 y4

Decidability criterion for uniformly well connected architectures

Theorem

Architectures with preordered information are decidable for CTL* specifications.

Proof.

x1 y1 x2 y2 x3 y3 x4 y4

Decidability criterion for uniformly well connected architectures

Theorem

Architectures with preordered information are decidable for CTL* specifications.

Proof.

x1 y1 x2 y2 x3 y3 x4 y4 y1 y2 y3 y4 a1 a2 a3 a4 x1 x2 x3 x4 x2 x3 x4 x3 x4 x4

Theorem: Kupferman-Vardi (LICS’01)

The synthesis problem with local strategies is decidable for pipeline archi- tectures and CTL∗ specifications (or tree-automata specifications) on all variables.

Outline

1

Uncomparable information

2

Uniformly well connected architectures

3

Well connected architectures

Well connected architectures

Definition

An architecture is well connected if, for each output variable y, the subarchitecture formed by E ∗−1(y) is uniformly well connected. u v w p p s t p p p x y z

Well connected architectures

Definition

An architecture is well connected if, for each output variable y, the subarchitecture formed by E ∗−1(y) is uniformly well connected. u v w p p s t p p p x y z v

Well connected architectures

Definition

An architecture is well connected if, for each output variable y, the subarchitecture formed by E ∗−1(y) is uniformly well connected. u v w p p s t p p p x y z u w

Well connected architectures

Definition

An architecture is well connected if, for each output variable y, the subarchitecture formed by E ∗−1(y) is uniformly well connected. u v w p p s t p p p x y z v

Well connected architectures

Theorem

One can decide whether an architecture is well-connected in polynomial time.

Well connected architectures

Theorem

One can decide whether an architecture is well-connected in polynomial time.

Well connected architectures

Theorem

One can decide whether an architecture is well-connected in polynomial time.

Well connected architectures

Theorem

One can decide whether an architecture is well-connected in polynomial time.

Rasala Lehman–Lehman 2004

One can solve the network information flow in the special case where there is a unique sink in polynomial time.

Well connected architectures

Theorem

There exists a well connected architecture which is not uniformly well connected.

Well connected architectures

Theorem

There exists a well connected architecture which is not uniformly well connected.

Lemma (Rasala Lehman–Lehman 2004)

If f 1, . . . , f n are pairwise independent functions of the form S2 → S, then n ≤ |S| + 1.

Well connected architectures

Theorem

There exists a well connected architecture which is not uniformly well connected.

Lemma (Rasala Lehman–Lehman 2004)

If f 1, . . . , f n are pairwise independent functions of the form S2 → S, then n ≤ |S| + 1. u w z1 z2 z3 z4 z12 z13 z14 z23 z24 z34

Well connected preordered architectures are undecidable

Theorem

The synthesis problem for LTL specifications and well connected, preordered information is undecidable.

Well connected preordered architectures are undecidable

Theorem

The synthesis problem for LTL specifications and well connected, preordered information is undecidable. w u v x y z0 q0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architectures are undecidable

Theorem

The synthesis problem for LTL specifications and well connected, preordered information is undecidable. w u v x y z0 q0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architectures are undecidable

Theorem

The synthesis problem for LTL specifications and well connected, preordered information is undecidable. w u v x y z0 q0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6 0q1p0{0, 1}ω #p+qCp#ω

Well connected preordered architectures are undecidable : The specification

w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architectures are undecidable : The specification

w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6 0q10{0, 1}ω #q+1C1#ω 0q′10{0, 1}ω #q′+1C1#ω

Well connected preordered architectures are undecidable : The specification

w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6 0q1p0{0, 1}ω #q+pC#ω 0q′1p′0{0, 1}ω #q′+p′C′#ω

Well connected preordered architectures are undecidable : The specification

w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6 0q1p0{0, 1}ω 0q1p0{0, 1}ω #q+pC#ω #q+pC′#ω u = v = ⇒ x = y

Well connected preordered architectures are undecidable : The specification

w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6 0q1p+10{0, 1}ω 0q+11p0{0, 1}ω #q+p+1C#ω #q+p+1C′#ω u = v + 1 = ⇒ C′ ⊢ C

Well connected preordered architectures are undecidable : The specification

w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6 0 . . . 01 u w u w u w u w u w w

Well connected preordered architectures are undecidable : A distributed implementation

w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architectures are undecidable : A distributed implementation

w u v x y z0 p0 p6 p p Cp q Cq z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architectures are undecidable : A distributed implementation

w u v x y z0 p0 p6 p p Cp q Cq 0 . . . 01 u u ⊕ w u w w u w u w u w u w u w w z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architectures are undecidable : Another distributed implementation

w u v x y z0 p0 p6 p p Cp q Cq 0 . . . 01 u u u ⊕ w w Y u ⊕ w u w u w u w u w u w w z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architectures are undecidable : The specification (end)

w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6 0 . . . 01 . . . u w

Well connected preordered architectures are undecidable: Masking one bit of u to y

Lemma

Let ub = 0qb1p0u′ and w = 0q1w′. Then (ˆ fz3, ˆ fz4)(u0[n], w[n]) = (ˆ fz3, ˆ fz4)(u1[n], w[n]) w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architectures are undecidable: Masking one bit of u to y

Lemma

Let ub = 0qb1p0u′ and w = 0q1w′. Then (ˆ fz3, ˆ fz4)(u0[n], w[n]) = (ˆ fz3, ˆ fz4)(u1[n], w[n]) w 0q1{0, 1}ω u p ∼ 0q01p0{0, 1}ω p + 1 ∼ 0q11p0{0, 1}ω v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architecures are undecidable: Enforcing output of the correct configuration

Lemma

For all q ≥ 0, u ∈ 0q1p0{0, 1}ω = ⇒ x = #q+pCp#ω w u v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architecures are undecidable: Enforcing output of the correct configuration

Lemma

For all q ≥ 0, u ∈ 0q1p0{0, 1}ω = ⇒ x = #q+pCp#ω w u p + 1 ∼ 0q11p0{0, 1}ω v x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architecures are undecidable: Enforcing output of the correct configuration

Lemma

For all q ≥ 0, u ∈ 0q1p0{0, 1}ω = ⇒ x = #q+pCp#ω w 0q1{0, 1}ω u p + 1 ∼ 0q11p0{0, 1}ω v 0q+11p0{0, 1}ω x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architecures are undecidable: Enforcing output of the correct configuration

Lemma

For all q ≥ 0, u ∈ 0q1p0{0, 1}ω = ⇒ x = #q+pCp#ω w 0q1{0, 1}ω u p + 1 ∼ 0q11p0{0, 1}ω v 0q+11p0{0, 1}ω p ∼ 0q01p0{0, 1}ω 0q+11p0{0, 1}ω 0q1{0, 1}ω x y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architecures are undecidable: Enforcing output of the correct configuration

Lemma

For all q ≥ 0, u ∈ 0q1p0{0, 1}ω = ⇒ x = #q+pCp#ω w 0q1{0, 1}ω u p + 1 ∼ 0q11p0{0, 1}ω v 0q+11p0{0, 1}ω p ∼ 0q01p0{0, 1}ω 0q+11p0{0, 1}ω 0q1{0, 1}ω x #p+q+1Cp#ω y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architecures are undecidable: Enforcing output of the correct configuration

Lemma

For all q ≥ 0, u ∈ 0q1p0{0, 1}ω = ⇒ x = #q+pCp#ω w 0q1{0, 1}ω u p + 1 ∼ 0q11p0{0, 1}ω v 0q+11p0{0, 1}ω p ∼ 0q01p0{0, 1}ω 0q+11p0{0, 1}ω 0q1{0, 1}ω x #p+q+1Cp#ω #p+q+1Cp#ω y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architecures are undecidable: Enforcing output of the correct configuration

Lemma

For all q ≥ 0, u ∈ 0q1p0{0, 1}ω = ⇒ x = #q+pCp#ω w 0q1{0, 1}ω u p + 1 ∼ 0q11p0{0, 1}ω v 0q+11p0{0, 1}ω p ∼ 0q01p0{0, 1}ω 0q+11p0{0, 1}ω 0q1{0, 1}ω x #p+q+1Cp#ω #p+q+1Cp#ω #p+q+1Cp#ω y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

Well connected preordered architecures are undecidable: Enforcing output of the correct configuration

Lemma

For all q ≥ 0, u ∈ 0q1p0{0, 1}ω = ⇒ x = #q+pCp#ω w 0q1{0, 1}ω u p + 1 ∼ 0q11p0{0, 1}ω v 0q+11p0{0, 1}ω p ∼ 0q01p0{0, 1}ω 0q+11p0{0, 1}ω 0q1{0, 1}ω x #p+q+1Cp#ω #p+q+1Cp#ω #p+q+1Cp#ω #p+q+1Cp+1#ω y z0 p0 p6 p z1 z2 z3 z4 p1 p2 p3 p4 p5 u1 w1 u2 w2 u3 w3 u4 w4 u5 w5 u6 w6

April Rasala Lehman and Eric Lehman. Complexity classification of network information flow problems. In SODA, pages 142–150, 2004.