Dissecting Design Choices for Power Efficient Continuous-time DS - - PowerPoint PPT Presentation

Dissecting Design Choices for Power Efficient Continuous-time DS Converters

Shanthi Pavan Indian Institute of Technology, Madras Chennai, India

2

Outline

• Introduction
• Architectural design choices
• Circuit techniques for low power
• Design details
• Measured results
• Conclusions

3

CTDSM in 1 minute

4

CTDSM in 1 minute

Hold

5

CTDSM in 1 minute

Digital Sequence Hold

6

CTDSM in 1 minute

Digital Filter

Hold

Does the number of quantizer levels matter?

7

CTDSM in 1 minute

HOLD

8

CTDSM in 1 minute : Antialiasing

HOLD

9

Loop Filter ADC DAC

Decimator

CTDSM : A System for all Seasons

“Digital”

Negative Feedback Industrially and Practically Relevant

10

(Too) Many Design Choices

ADC DAC Loop Filter

Order Sampling rate Quantizer Levels

11

Curse of Too Many Choices

• Single bit quantizer + high OSR

– Or multibit quantizer + low OSR?

• Flash ADC

– Or SAR ADC?

• NRZ DAC

– Or Switched capacitor DAC for low jitter?

12

Buridan’s Ass

Dies of starvation

Courtesy : Inspirehep.net

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DS Designer …

Dies of thirst!!

Courtesy : Inspirehep.net

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Motivation

• Aim : Audio DSM with > 100 dB DR

– 0.18µm CMOS technology – As low power as possible

• Low distortion (~100 dB) audio DS converters

– Typically realized with discrete-time, multi-bit loops

15

Single-bit versus Multibit Modulators

16

u v

DAC

Loop Filter

ADC

Quantizer : 1-bit versus 4-bit

4-bit quantizer needs half the OSR to achieve same in-band noise (Baseline : 3rd Order Single-bit DSM, OSR =128)

17

ADC Resolution

• 4 bit ADC
• 15x more comparators @ 1/2 speed
• 7x more ADC power, 15x more area
• 15x loop filter & clock path loading

u v

DAC

Loop Filter

ADC

18

Comparator Random Offset

R R R R y

Thermometer to Binary Digital Output clk clk clk

§ Increased in-band noise § Reduced stable amplitude

u v

DAC

Loop Filter

ADC

19

SNDR with Random Offset

Third-order Modulator 16-level Quantizer

20

u v

DAC

Loop Filter

ADC

Loop Filter

• Loop filter should swing full-scale
• Difficult in high-speed designs

21

u v

DAC

Loop Filter

Loop Filter

• Comparator offset is benign
• Driving the 1-bit quantizer

– Loop filter’s last stage simpler to design

– Particularly useful at high speeds

22

u v

DAC

Loop Filter

ADC

DAC : 1-bit versus 4-bit

• 4 bit DAC

– Needs Dynamic Element Matching – DEM adds excess delay & power A single bit quantizer consumes lesser power though it operates at 2x the speed

23

Single-bit CTDSM Issues : Clock Jitter

u L(s)

ADC DAC

v[n]

clk_adc clk_dac edac eadc

Jittery clock à equivalent to error at the input

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Single-bit CTDSM Issues : Clock Jitter

u L(s)

ADC DAC

v[n]

clk_adc clk_dac edac eadc

Large jitter error à rail-to-rail feedback waveform

25

u v

DAC

Loop Filter

ADC

Single-bit CTDSM Issues : Filter Linearity

ffr

ffr

ffr

26

Increased loop filter power dissipation needed to achieve linearity

Single-bit CTDSM Issues : Filter Linearity

u v

DAC

Loop Filter

ADC

ffr

ffr

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Summary so far …

§ Single bit operation – Very efficient quantizer – Easy to drive – Sensitive to clock jitter – Loop filter needs to handle large swings

• Increased power dissipation

28

DAC F(z) u

v

Loop Filter

u(t)

Improved Single-bit CTDSM : FIR Feedback

Single-bit ADC FIR filter in the feedback path

FIR DAC

29

DAC F(z) u

v

Loop Filter

u(t)

Improved 1-bit CTDSM : FIR Feedback

Height of steps à Greatly reduced à Reduced jitter sensitivity

30

Improved 1-bit CTDSM : FIR Feedback

f (kHz)

• 20

10 20 30 40

• 40
• 60
• 80
• 100
• 120
• 140
• 160

PSD (dB)

Ideal 1-bit ADC + 1-bit DAC 12-level 1-bit ADC + 12-tap FIR

31

FIR DAC and Element Mismatch

Semi-digital Implementation Mismatch does not lead to non-linearity

D D

DAC DAC

D

DAC DAC

v[n] v1(t)

Single-bit DACs (inherently linear)

v[n] v1(t)

DAC F(z)

1-bit Multibit

32

Improved 1-bit CTDSM : FIR Feedback

u(t)-v1(t) à very small à Improved loop filter linearity

DAC F(z) u

v

Loop Filter

u(t)

33

Summary so far …

§ Single bit ADC + FIR DAC –Low power ADC, easy to drive –Inherently linear DAC, no DEM –Low jitter sensitivity –Improved loop filter linearity Benefits of single-bit operation Benefits of multi-bit operation

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Key Takeaway

Multi Bit DSM üTolerates jitter üLow power loop filter

Single Bit DSM

üLow power ADC üInherently linear DAC

Single-bit ADC + FIR DAC combines benefits of 1-bit and multi-bit operation

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Single-bit ADC + FIR DAC

§ but dormant for a long while – why? § (?) Multibit & DEM well established by 2003 § (?) More difficult to understand § (?) Stability

Slide 35

DAC F(z) u

v

Loop Filter

u(t) (G)old Idea :

B.Putter, ISSCC 2003; O.Oliaei, TCAS-II 2003

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FIR DAC Summary

• Low power loop ADC
• Simple DAC – no DEM
• Multilevel feedback waveform

– Improved loop filter linearity – Reduced clock jitter sensitivity

• Performance benefits of a multibit quantizer

– But with low power

37

FIR DAC : Number of taps

• More FIR taps à Better filtering
• àReduced clock jitter sensitivity, better linearity

What prevents us from using a large number of taps ? (say 1000)

38

Increasing FIR Length

4 taps Vin v1 verror verror

Large verror due to inadequate filtering of shaped quantization noise

39

Increasing FIR Length

12 taps Vin v1 verror

Smaller verror due to better filtering

verror

40

Increasing FIR Length

64 taps Vin v1 verror

Large verror due to higher phase shift

verror

41

Error Signal Magnitude

Better filtering of shaped quantization noise More delay between input and feedback waveform

12 taps chosen in this design

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Modulator Architecture

Third Order CIFF-B Prototype

• +
• +
• +

D

Compensating FIR DAC

• u

Main FIR DAC

DAC1

u

DAC

43

FIR Feedback : More Benefits

44

1/f Noise in CTDSMs

R D=±1 fs Gota R C C R R Rest of Loop Filter Dominant source of 1/f noise vi

• vi
• vdac

vdac

45

1/f Noise Mitigation in CTDSMs

R Gota R C C R R Brute Force Solution § Increase device sizes à Increased parasitics à Reduced loop gain à Higher distortion à Higher area vi

• vi
• vdac

vdac

46

1/f Noise Mitigation in CTDSMs

R Gota R C C R R Chopping § Modulates 1/f noise out of the signal band fch fch vi

• vi
• vdac

vdac

47

Chopping in CT ΔƩ-Modulators

48

Chopping in a CTΔƩM

R D=±1 fs Gota R C C R R Rest of Loop Filter vin fc fc Chopped Integrator

49

Chopping in a CTΔƩM

vd

• vdac

vdac

50

chop = 1

Chopping transition at t = t1 vx(t1)

• vx(t1)

t = t1-

t = t1

vx(t) ≈ vd(t) RGota

51

chop = 1 chop = -1

vx(t) ≈ vd(t) RGota

t = t1- t = t1+

vx(t1)

• vx(t1)

vx(t1)

• vx(t1)

52

DV = -2vx(t1)

At EVERY transition of the chopping clock

vx(t1)

• vx(t1)

vx(t1)

• vx(t1)

53

At EVERY transition of the chopping clock

Error charge due to chopping vx(t1)

• vx(t1)
• vx(t1)

vx(t1)

54

Error Model of a Chopped Integrator

OTA input parasitic Virtual Ground Voltage Sampled at chopping edge

vx ≈ vd RGota

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fch fch

Error current injected at every edge of fch àSampling the virtual ground at 2fch àError proportional to Ci/RGota

Ci Co Ci

56

fch fch vd

• vd

fs/2

• 120
• 60

PSD (dB)

fch 2fch 3fch 4fch Aliasing

Signal band

57

fch fch Output parasitic switched at every edge of fch

Co Co

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Chopped Co : Equivalent Resistor

fch

Co Co

VDC

+

• RDC

RDC

RDC = 1 2fchCo

VDC

+

• Reduced Integrator DC Gain

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Chopping in CTDSMs : Summary

§ Aliases shaped noise from multiples of 2fch

− Inversely proportional to GotaR − Inversely proportional to number

• f quantizer levels

u

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Chopping in CTDSMs : Summary

§ Reduced integrator gain

− Switched capacitor resistor at the output 1/(4fchCo) − More 1/f noise from rest of loop

u

61

Chopping in CTDSMs : Summary

Solutions

Increase GotaR

✗ 20dB reduction of alias noise dissipates 10x power

Increase number of quantizer levels ✗ 20dB reduction of alias noise needs 10x the number of levels

62

FIR Feedback DAC

fs/N 2fs/N 3fs/N 4fs/N

N taps

63

FIR Feedback and Chopping

fs/N 2fs/N 3fs/N 4fs/N

N taps fch = fs 2N

Chopping frequency chosen as fs/2N à Nulls at multiples of 2fch à Reduced aliasing of shaped noise

64

1-bit quantizer & FIR Feedback : Summary

N taps

ü Reduced jitter sensitivity ü Improved integrator linearity ü Reduced chopping artifacts ü Inherently linear DAC

65

Architecture and Circuit Design

66

3rd Order CTDSM Architecture

CIFF-B Loop Filter Active-RC Integrators Input feed forward 12 tap FIR DAC 12 tap compensation DAC

67

3rd Order CTDSM Architecture

Chopped at fs/24 = 256kHz

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3rd Order CTDSM Architecture

Semidigital Implementation Worst case attenuation > 35dB

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Monte Carlo : 1% random tap mismatch

Attenuation > 35dB

70

OTA Design

71

2 Stage Feedforward Compensated OTA

NMOS/PMOS input pair à 2x gm for the same current Cascodes à High DC gain 2nd Stage

Feedforward

72

CMFB compensation capacitors Small fraction (c1) inside chopper àCompensation during chop transitions

73

Measurement Results

74

Die Photo & Layout Snapshot

UMC 180nm CMOS process (Europractice)

75

Dynamic Range Plot

100 75 50 25 SNR/SNDR (dB) Input (dBFS)

• 100
• 80
• 60
• 40
• 20

SNDR SNR

Peak SNR: 99.3 dB Peak SNDR: 98.5 dB DR : 103.5 dB

98.0 98.5 99.0

• 4.5
• 4.0
• 3.5
• 3.0

76

PSD at Peak SNDR

0.01 1 0.1 10 100 1000

• 150
• 100
• 50

PSD (dBFS) f (kHz) Input -3.4 dBFS @ 6kHz HD3 = 107.6 dB HD2 = 118.9 dB SNR: 99.3 dB SNDR: 98.5 dB Chopping tone

77

Low Frequency PSD

• 100
• 110
• 120
• 130
• 150

PSD (dBFS)

• 140

1 10 100 1K 10K f (Hz)

No chopping No chopping

78

Low Frequency PSD

• 100
• 110
• 120
• 130
• 150

PSD (dBFS)

• 140

1 10 100 1K 10K f (Hz)

fch = fs = 6.144 MHz

79

Low Frequency PSD

• 100
• 110
• 120
• 130
• 150

PSD (dBFS)

• 140

1 10 100 1K 10K f (Hz)

fch = fs/24 = 256 kHz

80

Low Frequency PSD

• 100
• 110
• 120
• 130
• 150

PSD (dBFS)

• 140

1 10 100 1K 10K f (Hz)

1/f corner ~ 3Hz

2nd Harm. 3rd Harm.

50Hz Harmonics

Tones

81

Effect of changing fch

512 1024 1536 2048 2560 3072

f (kHz)

• 10
• 20
• 30
• 40
• Mag. (dB)

Increased Aliasing

fch = fs/24 = 256kHz fch = fs/20 = 312.2kHz

82

PSD Comparison : fc= fs/24 & fs/20

5 10 15 20

• 135
• 130
• 125
• 120
• 115
• 110

f (kHz) PSD (dBFS)

fch = fs/20 fch = fs/24

83

PSD Comparison

• 100
• 110
• 120
• 130
• 150

PSD (dBFS)

• 140

1 10 100 1K 10K f (Hz)

fch = fs/24

No chopping, devices 16x larger ([3], JSSC 2014) 20dB

84

This work [3] JSSC 2014 [4] ISSCC 2008 [5] VLSI 2015 [6] ASSCC 2014

BW (kHz)

24 24 20 24 24

Feature Size (nm)

180 180 45 65 28

Supply (V)

1.8 1.8 1.1 1.1 1.1

Power (µW)

280 280 1200 121 9900

Peak SNDR (dB)

98.5 98.2 76.5 85 98.5

DR (dB)

103.6 103 91.7 88 100.6

SFDR (dB)

107.6 106 80.5 90 102.6

Chop Freq. (kHz)

256

• 46
• FoMSNDR (fJ/lvl)

85 88 500 173.4 342

FoMSchreier (dB)

177.8 177.5 148.5 168 172

Performance Summary and Comparison

85

A Tale of 4 ADCs

§ Multi-bit (4-bit ADC in the loop)

§ ESSCIRC 2007, JSSC 2008

§ Single-bit ADC with linearity enhancement

§ ESSCIRC 2009, JSSC 2010

§ Single-bit ADC + 12-tap FIR DAC

§ ASSCC 2013, JSSC 2014

§ Single-bit ADC + 12-tap FIR DAC + Chopping

§ ISSCC 2016, JSSC 2017

§ Same process, same design group

86

Multi-bit Modulator

• Third order CIFF loop
• 4-bit flash ADC
• OSR = 64 ( Clock Rate = 3.072 MHz)
• NRZ Resistive DAC
• Data Weighted Averaging

87

Single-bit Modulator

• Third order CIFF loop
• 1-bit ADC
• OSR = 128 ( Clock Rate = 6.144 MHz)
• NRZ Resistive DAC

88

Modulator Architecture

u y

1 s

DAC

k3

1 s

v

ADC

1 s

k2 k1

First integrator has to be very linear

ffr

ffr

89

The Assisted-Opamp Integrator

4Vref R

Gota

C R R

u v

u R

± Vref

R

gm DAC

u R

u v ± Vref

R

Assistant

90

1-bit + FIR DAC Based Modulator

• Third order CIFF-B loop
• 1-bit ADC + 12-tap FIR DAC
• OSR = 128 ( Clock Rate = 6.144 MHz)
• NRZ Resistive DAC

91

Modulator Architecture

• +
• +
• +

D

Compensating FIR DAC

• u

Main FIR DAC

DAC1

u

DAC

92

1-bit + FIR DAC + Chopping

• Third order CIFF-B loop
• 1-bit ADC + 12-tap FIR DAC
• OSR = 128 ( Clock Rate = 6.144 MHz)
• NRZ Resistive DAC
• First integrator chopped at fs/24
• ISSCC 2016

93

1-bit + FIR + chopping 1-bit ADC + FIR DAC 1-bit ADC 4-bit ADC

BW (kHz)

24 24 24 24

Feature Size (nm)

180 180 180 180

Supply (V)

1.8 1.8 1.8 1.8

Power (µW)

280 280 110 121

Peak SNDR (dB)

98.5 98.2 88 90.8

DR (dB)

103.6 103 91.7 88

SFDR (dB)

107.6 106 95 94

FoMSNDR (fJ/lvl)

85 88 111 89

FoMSchreier (dB)

177.8 177.5 171.4 173.7

Performance Summary and Comparison

94

Conclusions

§ FIR feedback

üSimple 1-bit ADC üReduced ADC power and area üSimplified clock distribution üInherently linear DAC à No DEM üRelaxes integrator linearity and jitter requirements üChopping for free üCombines benefits of 1-bit and multi-bit operation üHighest Schreier FoM reported