Dissecting Design Choices for Power Efficient Continuous-time DS - PowerPoint PPT Presentation

Dissecting Design Choices for Power Efficient Continuous-time DS Converters Shanthi Pavan Indian Institute of Technology, Madras Chennai, India

Outline • Introduction • Architectural design choices • Circuit techniques for low power • Design details • Measured results • Conclusions 2

CT DS M in 1 minute 3

CT DS M in 1 minute Hold 4

CT DS M in 1 minute Hold Digital Sequence 5

CT DS M in 1 minute Digital Filter Hold Does the number of quantizer levels matter? 6

CT DS M in 1 minute HOLD 7

CT DS M in 1 minute : Antialiasing HOLD 8

CT DS M : A System for all Seasons “ Digital ” ADC Loop Filter Decimator DAC Negative Feedback Industrially and Practically Relevant 9

(Too) Many Design Choices Order Sampling rate Loop ADC Filter Quantizer Levels DAC 10

Curse of Too Many Choices • Single bit quantizer + high OSR – Or multibit quantizer + low OSR? • Flash ADC – Or SAR ADC? • NRZ DAC – Or Switched capacitor DAC for low jitter? 11

Buridan’s Ass Dies of starvation 12 Courtesy : Inspirehep.net

DS Designer … Dies of thirst!! 13 Courtesy : Inspirehep.net

Motivation • Aim : Audio DSM with > 100 dB DR – 0.18 µ m CMOS technology – As low power as possible • Low distortion (~100 dB) audio DS converters – Typically realized with discrete-time, multi-bit loops 14

Single-bit versus Multibit Modulators 15

Quantizer : 1-bit versus 4-bit Loop Filter u ADC v DAC 4-bit quantizer needs half the OSR to achieve same in-band noise (Baseline : 3 rd Order Single-bit DSM, OSR =128) 16

ADC Resolution Loop Filter u ADC v DAC • 4 bit ADC - 15x more comparators @ 1/2 speed - 7x more ADC power, 15x more area - 15x loop filter & clock path loading 17

Comparator Random Offset Loop Filter u ADC v clk R DAC Thermometer to Binary clk R Digital Output clk R § Increased in-band noise § Reduced stable amplitude R y 18

SNDR with Random Offset Third-order Modulator 16-level Quantizer 19

Loop Filter Loop Filter u ADC v DAC • Loop filter should swing full-scale • Difficult in high-speed designs 20

Loop Filter Loop Filter u v DAC • Comparator offset is benign • Driving the 1-bit quantizer – Loop filter’s last stage simpler to design – Particularly useful at high speeds 21

DAC : 1-bit versus 4-bit Loop Filter u ADC v A single bit quantizer consumes DAC lesser power though it operates at 2x the speed • 4 bit DAC – Needs Dynamic Element Matching – DEM adds excess delay & power 22

Single-bit CTDSM Issues : Clock Jitter clk_adc e adc u v[n] L(s) ADC DAC e dac clk_dac Jittery clock à equivalent to error at the input 23

Single-bit CTDSM Issues : Clock Jitter clk_adc e adc u v[n] L(s) ADC DAC e dac clk_dac Large jitter error à rail-to-rail feedback waveform 24

Single-bit CTDSM Issues : Filter Linearity Loop Filter u ADC v ffr ffr DAC 25 ffr

Single-bit CTDSM Issues : Filter Linearity Loop Filter u ADC v ffr ffr DAC Increased loop filter power dissipation needed to achieve linearity 26

Summary so far … § Single bit operation – Very efficient quantizer – Easy to drive – Sensitive to clock jitter – Loop filter needs to handle large swings • Increased power dissipation 27

Improved Single-bit CTDSM : FIR Feedback u Loop Filter v DAC F(z) u(t) Single-bit ADC FIR DAC FIR filter in the feedback path 28

Improved 1-bit CTDSM : FIR Feedback u Loop Filter v DAC F(z) u(t) Height of steps à Greatly reduced à Reduced jitter sensitivity 29

Improved 1-bit CTDSM : FIR Feedback 0 -20 -40 -60 1-bit ADC PSD (dB) -80 + 1-bit DAC -100 12-level -120 -140 Ideal 1-bit ADC -160 + 12-tap FIR 0 10 20 30 40 30 f (kHz)

FIR DAC and Element Mismatch F(z) DAC v 1 (t) v[n] 1-bit Multibit Single-bit DACs (inherently linear) v[n] D D D DAC DAC DAC DAC v 1 (t) Semi-digital Implementation Mismatch does not lead to non-linearity 31

Improved 1-bit CTDSM : FIR Feedback u Loop Filter v DAC F(z) u(t) u(t)-v 1 (t) à very small à Improved loop filter linearity 32

Summary so far … § Single bit ADC + FIR DAC –Low power ADC, easy to drive –Inherently linear DAC, no DEM –Low jitter sensitivity –Improved loop filter linearity Benefits of single-bit operation Benefits of multi-bit operation 33

Key Takeaway Multi Bit DSM Single Bit DSM ü Tolerates jitter ü Low power ADC ü Low power loop ü Inherently linear DAC filter Single-bit ADC + FIR DAC combines benefits of 1-bit and multi-bit operation 34

Single-bit ADC + FIR DAC u Loop Filter v DAC u(t) (G)old Idea : F(z) B.Putter, ISSCC 2003; O.Oliaei, TCAS-II 2003 § but dormant for a long while – why? § (?) Multibit & DEM well established by 2003 § (?) More difficult to understand § (?) Stability 35 Slide 35

FIR DAC Summary • Low power loop ADC • Simple DAC – no DEM • Multilevel feedback waveform – Improved loop filter linearity – Reduced clock jitter sensitivity • Performance benefits of a multibit quantizer – But with low power 36

FIR DAC : Number of taps What prevents us from using a large number of taps ? (say 1000) • More FIR taps à Better filtering • à Reduced clock jitter sensitivity, better linearity 37

Increasing FIR Length V in v 1 v error 4 taps v error Large v error due to inadequate filtering of shaped quantization noise 38

Increasing FIR Length V in v 1 v error 12 taps v error Smaller v error due to better filtering 39

Increasing FIR Length V in v 1 v error 64 taps v error Large v error due to higher phase shift 40

Error Signal Magnitude Better filtering of shaped quantization noise 12 taps chosen in this design More delay between input and feedback waveform 41

Modulator Architecture -u u - - - D + + + Compensating FIR DAC DAC Main FIR DAC DAC1 Third Order CIFF-B Prototype 42

FIR Feedback : More Benefits 43

1/f Noise in CTDSMs R -v dac C f s v i R Rest of G ota D= ± 1 Loop Filter -v i R C v dac R Dominant source of 1/f noise 44

1/f Noise Mitigation in CTDSMs R -v dac C Brute Force Solution Increase device sizes § v i R à Increased parasitics G ota à Reduced loop gain à Higher distortion -v i R à Higher area C v dac R 45

1/f Noise Mitigation in CTDSMs R -v dac C v i R Chopping G ota Modulates 1/f noise out of § the signal band -v i R f ch f ch C v dac R 46

Chopping in CT Δ Ʃ -Modulators 47

Chopping in a CT Δ Ʃ M Chopped Integrator R C f s R Rest of v in G ota D= ± 1 Loop Filter R f c f c C R 48

Chopping in a CT Δ Ʃ M -v dac v d v dac 49

chop = 1 t = t 1 v x (t) ≈ v d (t) RG ota Chopping transition t = t 1 - at t = t 1 v x (t 1 ) -v x (t 1 ) 50

chop = -1 chop = 1 v x (t) ≈ v d (t) RG ota t = t 1 + t = t 1 - v x (t 1 ) -v x (t 1 ) v x (t 1 ) -v x (t 1 ) 51

At EVERY transition of the chopping clock D V = -2v x (t 1 ) v x (t 1 ) -v x (t 1 ) v x (t 1 ) -v x (t 1 ) 52

At EVERY transition of the chopping clock Error charge due to chopping v x (t 1 ) v x (t 1 ) -v x (t 1 ) -v x (t 1 ) 53

Error Model of a Chopped Integrator Virtual OTA input Ground parasitic Voltage Sampled at chopping edge v d v x ≈ RG ota 54

C i C o C i f ch f ch Error current injected at every edge of f ch à Sampling the virtual ground at 2f ch à Error proportional to C i /RG ota 55

v d -v d f ch f ch Signal band 0 PSD (dB) Aliasing -60 -120 0 f s /2 f ch 2f ch 3f ch 4f ch 56

C o C o f ch f ch Output parasitic switched at every edge of f ch 57

Chopped C o : Equivalent Resistor 1 R DC = C o 2f ch C o R DC + + V DC V DC - - R DC C o f ch Reduced Integrator DC Gain 58

Chopping in CTDSMs : Summary § Aliases shaped noise from multiples of 2f ch − Inversely proportional to G ota R − Inversely proportional to number of quantizer levels u 59

Chopping in CTDSMs : Summary § Reduced integrator gain − Switched capacitor resistor at the output 1/(4f ch C o ) − More 1/f noise from rest of loop u 60

Chopping in CTDSMs : Summary Solutions Increase G ota R ✗ 20dB reduction of alias noise dissipates 10x power Increase number of quantizer levels ✗ 20dB reduction of alias noise needs 10x the number of levels 61

FIR Feedback DAC N taps f s /N 2f s /N 3f s /N 4f s /N 62

FIR Feedback and Chopping N taps f s /N 2f s /N 3f s /N 4f s /N f ch = f s 2N Chopping frequency chosen as f s /2N à Nulls at multiples of 2f ch à Reduced aliasing of shaped noise 63

1-bit quantizer & FIR Feedback : Summary N taps ü Reduced jitter sensitivity ü Improved integrator linearity ü Reduced chopping artifacts ü Inherently linear DAC 64

Architecture and Circuit Design 65

3 rd Order CTDSM Architecture CIFF-B Active-RC Loop Filter Integrators 12 tap 12 tap compensation DAC FIR DAC Input feed forward 66

3 rd Order CTDSM Architecture Chopped at f s /24 = 256kHz 67