Diplomatic Design Patterns Wesley Terpstra Yunsup Lee A TileLink - - PowerPoint PPT Presentation

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Diplomatic Design Patterns Wesley Terpstra Yunsup Lee A TileLink - - PowerPoint PPT Presentation

Nov 24, 2022 605 likes •923 views

Henry Cook Diplomatic Design Patterns Wesley Terpstra Yunsup Lee A TileLink Case Study 10/14/2017 Rocket-Chip Ecosystem Diplomacy TileLink Design Patterns Agenda DRYing out Parameterization Generation with a View

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Diplomatic Design Patterns

A TileLink Case Study

Henry Cook Wesley Terpstra Yunsup Lee 10/14/2017

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SiFive Confidential

  • Rocket-Chip Ecosystem
  • Diplomacy
  • TileLink
  • Design Patterns
  • DRYing out Parameterization
  • Generation with a View
  • Compositional Cake
  • Deployment

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Agenda

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  • Chisel
  • A Domain-Specific Language for hardware construction embedded in Scala
  • Rocket-Chip
  • A collection of hardware generators implemented in Chisel
  • Diplomacy
  • A Scala framework for negotiating parameters between Chisel generators
  • TileLink
  • A parameterized chip-scale shared-memory interconnect protocol

The Rocket-Chip Ecosystem for RISC-V

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Diplomacy

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  • We’d like to be able to see everything that will be in the system

before we even start to emit any hardware descriptions

  • How early can we detect misconfiguration?
  • <> considered harmful
  • wire width inference can mask problems
  • Generators are nice...
  • but parameterization itself is a source of complexity
  • but each generator needs to agree with the others about what to generate

When Chisel Isn’t Enough

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  • Graphical abstraction of interconnectivity
  • Directed Acyclic Graph (DAG)
  • Node
  • point where parameterized hardware is going to be generated
  • Edge
  • a directed pairing between a master and slave interface
  • Modules may have many nodes and nodes may have many edges

Diplomatic Parameterization

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Simple Example Graph

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SiFive Confidential

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Actual (small) Rocket-Chip Graph

Tile TL to AXI Peripherals TL to AXI AXI to TL

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  • The cardinality of sources connected to a particular sink (transitive)
  • The cardinality of sinks connected to a particular source (transitive)
  • The type and size of operations issues by each master and slave
  • The type and size of operations allowed on a particular address
  • Other properties governing allowed behavior on particular regions

(e.g. modifiability, executability, cacheability)

  • Ordering requirements on operations over subgraphs (e.g. FIFO)
  • Presence of certain fields within control wire bundles
  • Widths of fields within with control or data wire bundles
  • Presence of entire virtual networks or channels

What Parameters Can Be Diplomatic?

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  • Two-phase elaboration
  • First, graph is created and parameters are negotiated (LazyModules)
  • Second, Chisel hardware is elaborated (Module implementations)
  • During the first (“diplomatic”) phase:
  • One set of parameters flow outwards from master to slave nodes
  • One set of parameters flow inwards from slave to master nodes
  • Adapter nodes can modify parameters flowing through them
  • All modules can place requirements on parameter values

How Diplomacy Negotiates

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  • What happens when negotiation fails?
  • Error at Scala runtime
  • What doesn’t happen?
  • Chisel elaboration
  • Verilog emission
  • Verilog compilation
  • Simulation execution
  • Waveform debugging

Short Circuiting the Debug Loop

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TileLink

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SiFive Confidential

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TileLink: Graphical Structure

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  • Directed Acyclic Graph (DAG) (again)
  • Agent (Node)
  • point where messages are created
  • Link (Edge)
  • a directed pairing between two agents’

master and slave interface

  • Modules may have many agents and

agents may have many links

TileLink: Graphical Structure

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SiFive Confidential

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TileLink: Directed Channels

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  • Spec defines threes levels of

conformance

  • Rocket-Chip uses Diplomacy to

achieve even finer granularity

  • Individual links specialized to the types
  • f messages sent

TileLink: Modularity

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  • Generality of interfaces
  • All agents use the same transaction structure
  • Scalability rules for hierarchy
  • DAG prevents deadlock
  • Strict prioritization of channels
  • Necessary for individual transactions to make

forward progress

  • Decoupled handshaking rules
  • Limit when and why messages can be rejected

TileLink: Composability

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  • Deadlock freedom and forward progress guarantees!
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SiFive Confidential

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TileLink: Transaction Structure

https://www.sifive.com/documentation/tilelink/tilelink-spec/

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Design Patterns

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  • Don’t Repeat Yourself
  • “Every piece of knowledge must have a single , unambiguous, authoritative

representation within a system”

DRYing out parameterization

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3 3 3 3 3 3 3 1 2 3

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SiFive Confidential

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Hardware Generation With A View

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  • Thin adapters that each serve a specific, orthogonalized function
  • Zero-cycle response time is allowed (support is actually mandatory)
  • Simplify verification at no design cost

Combinational Composition

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  • Modify control signals
  • fragment burst messages into a series of single beat messages

Combinational Composition

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  • Manage inter-message transaction requirements
  • enforce FIFO ordering across a series of messages and responses
  • Modify message field widths
  • widen the width of the data bus plane
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  • Decoupled nature of TileLink interfaces makes it easy to insert

buffering at arbitrary point in the graph

Sequential Composition

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  • Any sub-graph can be swapped out for a different sub-graph that

provides the same properties

  • Inserting caches (or chains of caches)
  • Filtering addresses into banks
  • Transparently crossing clock domains
  • Transparently converting between protocols

Hierarchical Composition

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  • Scala traits
  • Interfaces that can provide concrete members
  • Support multiple inheritance
  • Build a system from layered components (cake pattern)
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Compositional Cake

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Deployment

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  • Piecewise conversion to Diplomatic TileLink and AMBA
  • using adapters between sub-graphs with different protocol versions
  • Started from slaves and moved inward to masters
  • Took about 6 months to complete
  • Only remaining non-diplomatic Modules are the top-level test

harness and leaf modules inside of the Rocket tiles

Rocket-Chip: 2017 Rewrite

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  • Automatic punching of IOs via cross-module edges
  • Ease arbitrary changes to granularity of module hierarchicalization
  • Conversion between clock domains
  • Cross at boundary of automatically inserted module wrappers
  • Lightweight support for interrupts and other simple types that need

to be routed to arbitrary locations, including to top-level IOs

  • Diplomatic RoCC

Future Work: Diplomacy

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  • Critical Word First for cache blocks
  • Richer performance hints
  • Cache coherence protocol parameterization
  • Deadlock freedom and forward progress proofs, formal models
  • ChipLink

Future Work: TileLink

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SiFive Confidential

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