Digital LLRF Technology on a TCA Platform Eugene Wu Northwestern - - PowerPoint PPT Presentation

Digital LLRF Technology

• n a μTCA Platform

Eugene Wu

Northwestern University Mentor: Tim Berenc Lee Teng Presentations August 10, 2016

2 Eugene Wu - Lee Teng Presentations - August 2016

Cavity

PA

FWD REV

Digital Signal Processing

• Field Control
• Fast Tuner Algorithm
• Slow Tuner Algorithm
• Calibration & Tune-Up
• etc.

Power Amplifier

Cavity System

IF LO CLK

LLRF Controller

Up-Converter

DAC ADC FWD REV CAV Reference

Down-Converters

ADC ADC ADC IF CAV ADC ADC Slow ADCs Fast ADCs DAC DAC Slow DACs RF LO i.e., Slow & Fast Tuners i.e., vibration sensors

beam

Motivation

• Low-level RF systems regulate the amplitude and phase of an RF cavity
• Present APS LLRF systems use analog hardware
• Long-term plans to upgrade to digital LLRF technology
• Goal of project: evaluate microTCA based hardware for digital applications

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• micro Telecommunications Computing Architecture (μTCA)

– Specifications-based hardware platform – Offers an ecosystem of various modules from multiple vendors – Used in high energy physics, digital LLRF, military, and telecommunications

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Hardware Components

• Vadatech AMC502 FPGA Carrier w/ Kintex-7 FPGA

– 2 FPGA Mezzanine Card (FMC) Slots

• D-TACQ ACQ420 Analog-to-Digital (ADC) FMC

– 16-bit, Four-channel, 2 Mega-samples per second (MSPS)

• D-TACQ AO400 Digital-to-Analog (DAC) FMC

– 18-bit, Four-channel, 1 MSPS

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FPGA FMC1 FMC0 CPU GbE microTCA Backplane

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FPGA Design

Signal Processing will go here

First Goal: Get ADC’s and DAC’s working

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ADC serial interface DAC serial interface

ADC and DAC Timing Diagrams

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VHDL Design

• Acquired reference designs from Vadatech and D-TACQ
• Modified to match hardware, wrote new DAC code

– e.g., 160 FMC pins x 2, DAC serial interface

• ~3600 lines of code
• Synthesize design and debug
• Use FPGA Integrated Logic Analyzer (ILA) to read internal

signals and debug

ModelSim simulation of DAC testbench

VHDL testbench for simulation/debugging

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Lab Setup

μTCA chassis Function generator and oscilloscope for testing FMC Front panel connector breakout Full view of lab

Real-time Data from FPGA

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Integrated Logic Analyzer Output

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ADC Data

32K Point FFT 10 kHz full-scale input

• n channel 1

𝑂𝑝𝑗𝑡𝑓 = 𝑂𝐺 ∗ 𝐶𝑋 ≅ 223 𝜈𝑊𝑆𝑁𝑇 Noise floor ~ -130 dBV2/Hz 𝑇𝑂𝑆 = 93 𝑒𝐶 Harmonics were found to be due to signal source

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DAC Output

ADC Input DAC Output FFT of DAC Output

(Stanford Research Systems SR785)

Summary

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• Successfully demonstrated use of ADC and DAC modules
• n a microTCA FMC carrier for baseband signal acquisition
• Future work

– Past application of baseband signal processing was for AM/PM noise suppression in APS storage ring RF systems (previous Lee Teng project using proprietary National Instruments hardware) – Intent is to migrate noise suppression algorithm to microTCA – Possibly start on signal processing next week – Ultimately need to transition into intermediate frequency signals for full digital LLRF