[PPT] - Di i l T Di i l T Digital Testing Digital Testing i i Lecture PowerPoint Presentation

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Di i l T i Di i l T i Digital Testing Digital Testing

L 4 Yi ld A l i & Yi ld A l i & Lecture Lecture 4: Yield Analysis & : Yield Analysis & Product Quality Product Quality

Instructor: Shaahin Hessabi Instructor: Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology Adapted from lecture notes prepared by the book authors Adapted from lecture notes prepared by the book authors

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Yield Analysis & Product Quality Yield Analysis & Product Quality Yield Analysis & Product Quality Yield Analysis & Product Quality

Yield and manufacturing cost

Yield and manufacturing cost g

Clustered defect yield formula

Yi ld i p

t Yi ld i p t

Yield improvement

Defect level

Test data analysis

Example: SEMATECH chip

Example: SEMATECH chip p p p p

Summary

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VLSI Chip Yield VLSI Chip Yield p

Defect: a physical imperfection in the processed wafer.

Defect: a physical imperfection in the processed wafer. A f d f f h h A f d f f h h

A manufacturing defect is a finite chip area with

A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the electrically malfunctioning circuitry caused by errors in the f b i i f b i i fabrication process. fabrication process.

A chip with no manufacturing defect is called a good chip.

Fraction (or percentage) of good chips produced in a

Fraction (or percentage) of good chips produced in a manufacturing process is called the manufacturing process is called the yield yield (Y) Y). . g p g p y ( )

Cost of a chip =

Cost of a chip = Cost of fabricating and testing a wafer

Cost of a chip =

Cost of a chip = ------------------------------------------------------ Yield * Number of chip sites on the wafer

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Clustered VLSI Defects Clustered VLSI Defects Clustered VLSI Defects Clustered VLSI Defects

Good chips Faulty chips Wafer Defects

Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77

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Yield Parameters Yield Parameters e d e e s e d e e s

Defect density (

Defect density (d ) = Average number of defects per ) = Average number of defects per y ( y ( ) g p ) g p unit of chip area unit of chip area

Chip area (

Chip area (A)

Clustering parameter (

Clustering parameter (α)

Negative binomial distribution of defects,

Negative binomial distribution of defects, p ( ) P b P b ( b f d f t hi ( b f d f t hi ) p (x x ) = ) = Prob Prob (number of defects on a chip = (number of defects on a chip = x x )

Γ (α+x +x ) (Ad /α) ) x ( ) ( ) ( ) = -------------

------------ . ----------------------
x !

x ! Γ (α) ) (1+Ad (1+Ad /α) ) α+x

+x

where Γ is the gamma function α =0, p (x , p (x ) is a delta function (max. clustering) = p (x ) i P i di ib i ( l i )

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α = , , p (x ) is Poisson distribution (no clustering)

∞

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Yield Equation Yield Equation Yield Equation Yield Equation

Y = Prob ( zero defect on a chip ) = p (0) Y = Prob ( zero defect on a chip ) = p (0)

Y = ( = ( 1 1 + + Ad Ad / / ) ) − α Y = ( = ( 1 1 + + Ad Ad / / α ) )

α

Example: Ad = 1.0, , α = 0.5, Y = 0.58 p ,

, Unclustered defects: α =

, Y , Y = e e - A

Ad

∞

Unclustered defects: α

, Y , Y e e

Example: Ad = 1.0, α =

, , Y = Y = 0.37 0.37

∞ ∞

p too pessimistic !

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Defect Level or Reject Ratio Defect Level or Reject Ratio Defect Level or Reject Ratio Defect Level or Reject Ratio

Defect level

Defect level (DL DL) is the ratio of faulty chips among the ) is the ratio of faulty chips among the chips that pass tests. chips that pass tests. p p p p

DL

DL is measured as is measured as parts per million parts per million (ppm ppm). ).

DL

DL is a measure of the effectiveness of tests. is a measure of the effectiveness of tests. DL DL is a measure of the effectiveness of tests. is a measure of the effectiveness of tests.

DL

DL is a quantitative measure of the manufactured is a quantitative measure of the manufactured product quality For commercial VLSI chips a product quality For commercial VLSI chips a DL DL product quality. For commercial VLSI chips a product quality. For commercial VLSI chips a DL DL greater than greater than 500 500 ppm ppm is considered unacceptable. is considered unacceptable. (normally: (normally: 500 500<DL< <DL<50 50) (normally: (normally: 500 500<DL< <DL<50 50)

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Determination of DL Determination of DL e e

e e
1.

1.

From field return data: Chips failing in the field are From field return data: Chips failing in the field are t d t th f t Th b f t d t th f t Th b f returned to the manufacturer. The number of returned to the manufacturer. The number of returned chips normalized to one million chips returned chips normalized to one million chips hi d i th hi d i th DL DL shipped is the shipped is the DL DL. .

How chips are returned:

How chips are returned: ili ili a. a. Failing acceptance test. Failing acceptance test. b. b. Failing system test. Failing system test. c. c. Failing maintenance test Failing maintenance test

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Determination of DL (cont’d) Determination of DL (cont’d) e e

(co

d) e e

(co

d)

2. 2.

From test data: Fault coverage of tests and chip fallout From test data: Fault coverage of tests and chip fallout t l d A difi d i ld d l i fitt d t t l d A difi d i ld d l i fitt d t rate are analyzed. A modified yield model is fitted to rate are analyzed. A modified yield model is fitted to the fallout data to estimate the the fallout data to estimate the DL DL. .

Th (d f l d b f l l i l Th (d f l d b f l l i l

Three parameters: (defect replaced by fault: electrical,

Three parameters: (defect replaced by fault: electrical, Boolean, or functional malfunctions) Boolean, or functional malfunctions)

Fault density

Fault density f f = average number of stuck = average number of stuck at faults per unit chip area at faults per unit chip area

Fault density,

Fault density, f f = average number of stuck = average number of stuck-at faults per unit chip area at faults per unit chip area

Fault clustering parameter,

Fault clustering parameter, β

Stuck

Stuck-

at fault coverage,

at fault coverage, T g

The modified yield equation:

Assuming that tests with

Assuming that tests with 100 100% fault coverage (T = % fault coverage (T =1 1. .0 0) )

Y (T ) = (1 + TAf /β) - β

g g ( g ( ) remove all faulty chips: remove all faulty chips: Y = Y Y = Y (1 1) = ( ) = (1 1 + + Af Af /β) ) – β

β yield, if T=

yield, if T=1 1 good chips good chips

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Defect Level Defect Level Defect Level Defect Level

Y (T ) - Y (1)

Faulty chips considered as good

Y (T ) Y (1) DL (T ) = --------------------

Y (T )

All chips which pass the

( β + + TAf ) β

All chips which pass the test, with coverage T

= 1 - --------------------

( β + Af ) β

Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, β is the fault clustering parameter. Af and β are determined by test data analysis.

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Example: SEMATECH Chip Example: SEMATECH Chip Example: SEMATECH Chip Example: SEMATECH Chip

Bus interface controller ASIC fabricated and tested

Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont at IBM, Burlington, Vermont

116

116, ,000 000 equivalent ( equivalent (2-

input NAND) gates

input NAND) gates

304

304-

pin package,

pin package, 249 249 I/O I/O

Clock:

Clock: 40 40MHz, some parts MHz, some parts 50 50MHz MHz

0.

.45 45μ CMOS, CMOS, 3 3. .3 3V, V, 9 9. .4 4mm x mm x 8 8. .8 8mm area mm area

Full scan,

Full scan, 99 99. .79 79% fault coverage % fault coverage

Advantest

Advantest 3381 3381 ATE, ATE, 18 18, ,466 466 chips tested at chips tested at 2 5MH t t l k MH t t l k 2. .5MHz test clock MHz test clock

Data obtained courtesy of Phil Nigh (IBM)

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Test Coverage from Fault Simulator Test Coverage from Fault Simulator Test Coverage from Fault Simulator Test Coverage from Fault Simulator

ge co coverag

at

at f fault Stuc Stuck- Vector n ctor number mber

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Vector n ctor number mber

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Measured Chip Fallout Measured Chip Fallout Measured Chip Fallout Measured Chip Fallout

The fallout The fallout fraction fraction

t

rises to rises to 0. .2386 2386, ,

ip fallou p fallou

because because the yield is the yield is

ured ch ed chi

near near 76 76%. %.

Meas Measu Vector n ctor number mber

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Model Fitting Model Fitting Model Fitting Model Fitting

Chi Chi f f ll t f f lt t

1-Y

Y (T

(T )

Chi Chip f fall llou

ut

t vs.

vs. f

fau ault lt co coverage

Y (1) = 1) = 0.76 0.7623 23 put uted ed 1 and com nd comp Y (T ) f ) for r Af Af = = 2 1 1 and and β = = 0 083 083 Measur easured ch ed chip f ip fallout

ut

fallou allout a Y (T ) f ) for r Af Af = = 2.1 1 and and β = = 0.083 083 Chip Chip f

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St Stuc uck-a k-at fault co fault coverage, T

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Computed DL Computed DL p

237 237,70 700 ppm (Y ppm (Y = = 76.23 76.23%) in ppm in ppm ect ct l level Def Defe St St k t f t f lt t (%) (%)

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St Stuc uck-a

at f

t fau ault lt co coverage (%) (%)

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Summary Summary

VLSI yield depends on two process parameters, defect

VLSI yield depends on two process parameters, defect density ( density (d ) and clustering parameter ( and clustering parameter (α) density ( density (d ) and clustering parameter ( and clustering parameter (α)

Yield drops as chip area increases; low yield means high

Yield drops as chip area increases; low yield means high cost cost cost cost

Fault coverage measures the test quality

Fault coverage measures the test quality D f l l ( D f l l (DL DL) j i i f hi ) j i i f hi

Defect level (

Defect level (DL DL) or reject ratio is a measure of chip ) or reject ratio is a measure of chip quality quality DL DL b d i d b l i f d b d i d b l i f d

DL

DL can be determined by an analysis of test data can be determined by an analysis of test data

For high quality:

DL <

DL < 500 500 ppm ppm, ,

fault coverage ~

fault coverage ~ 99 99% %

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