Design of a Flexible Open Platform for High Performance Active - - PowerPoint PPT Presentation

Jonathan Turner - 10/25/99

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

1

Design of a Flexible Open Platform for High Performance Active Networks

Sumi Choi, Dan Decasper, John Dehart, Ralph Keller, John Lockwood, Jonathan Turner,Tilman Wolf Washington University Applied Research Lab http://www.arl.wustl.edu/arl/

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2 Jonathan Turner - 9/22/99

Motivation

GTechnology advances adding new functionality to

internet routers.

» logic capabilities growing much faster than IO » packet classification, per flow queueing becoming common » single chip packet processing engines with 16 processors now becoming available

GApplication-specific processing in routers could

become routine.

» active networking is one way to exploit trend » alternative model

–signalling and resource reservation –packet classification and flow-specific routing

GKey challenge is application software. GNeed better experimental platforms for researchers.

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Towards an Open Internet Router

GModular components.

» ability to swap components - both hardware and software

– routing, signalling, management software – address lookup and packet classification – queueing and packet scheduling

» open, documented and straightforward interfaces

GDynamic insertion of application-specific processing.

» active networking model and others

GHigh performance.

» gigabit links and scalability to large numbers of ports » packet processing rates of at least a million/ second per link » application-specific processing on large fraction of traffic » need credible demonstrations to influence commercial practice

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Active Router Hardware

ANPEs IPPs LCs

Switch

LCs ANPEs OPPs CP AN Processing Element

APIC

Pentium Sys. FPGA 32-64 MB Cache NB

Input Port Processor

VCI VCI OUT

Control Processor

• global coordination & control
• routing & signalling protocols
• build routing tables and other

information needed by SPCs

• first level code server
• reprogrammable for active

processing

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Cell Processing

ANPEs IPPs LCs

Switch

LCs ANPEs OPPs CP

3 4 6 4

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Packet Processing

ANPEs IPPs LCs

Switch

LCs ANPEs OPPs CP

9 9 9

Sys. FPGA

APIC

Pentium Cache NB

2 6 2 6 2 6

Sys. FPGA

APIC

Pentium Cache NB

9 9 9

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Principal Data Flows Through PE Kernel

G Std. proc. for “ plain” IP packets.

» classification & routing, header processing, output queueing

Packet Classification and Routing Driver SAPF Packet IPv4/6 Header Processing

Packet + Flow Id

Packet Scheduler Active Function Dispatcher Resource Controller Selector/ Dispatcher IP Packets Driver

Active Packets Plain Packets

Kernel Plugins . . .

. . . . . .

. . . . . . . . .

G Active packets move through configured kernel plugins.

» active function dispatcher passes packets to instances of plugin objects » instantiates objects or triggers download of plugin class, as needed » streamlined processing of SAPF packets using pre-established state

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anetd Java VM

ANTS

Active Plugin Loader

Plugin Requestor Plugin DB Controller Policy Controller Security Gateway

ANN Manager

Plugin DB Key DB

Routing & Signalling

Control Processor Kernel

Code Server Code Server

Active Code DB

Kernel

Active Plugin Loader Plugin Requestor Security & Policy Controller

Switch Fabric

Kernel

Active Plugin Loader Plugin Requestor Security & Policy Controller

Processing Elements

. . .

Policy Rules

System Level Software Organization

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I O I O I O I O SE SE SE SE O I O I O I O I

Processor Module APIC System FPGA Connectors Optoelectronics Transmission Coder & Decoder Fiber jumper to front panel Main Circuit Board

Physical Configuration

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Field Programmable Port Extender Field Programmable Port Extender

Network Interface Device Reprogrammable

• App. Device

(250Kg+100Kb)

SDRAM

(32 MB)

SRAM

(1 MB)

Utopia Interface (3.2 Gb/s) Utopia Interface (3.2 Gb/s)

SRAM

(1 MB)

SDRAM

(32 MB)

64 100 MHz 32 32 64 100 MHz 6.4 Gb/s

Line Card PE

G Stackable port card

» can be combined with PE

G Programmable hardware

» FPGA technology » flexible memory config. » change on-the-fly

G Reprogrammable

Application Device (RAD)

» fully reprogrammable » four separate memory interfaces » memory bw: 2.4GB/ s

G Network Interface Device

(NID)

» relatively static » adapt for different line cards

G Variety of applications

» address lookup & packet class. » per flow queueing » traffic management » hardware plugins

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Conclusions

GHigh performance active networking need not be an

• xymoron.

» scalable systems with gigabit links and terabit throughputs are possible with current/ near-term technology » on-going technology improvements will make AN economically viable

GNeed to focus on active application development. GNeed better abstractions, tools, APIs for developers. GEffective & open experimental platforms are essential.

» provide realistic testbed » provide more convincing demonstrations » enable system researchers and developers to build on each

• thers efforts

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Credits

Sumi Choi Dan Decasper Ralph Keller John Dehart Tilman Wolf John Lockwood