Dept. Computer Architecture Universidad de Mlaga (Spain) - - PowerPoint PPT Presentation

SONIA GONZALEZ-NAVARRO AND JAVIER HORMIGO

• Dept. Computer Architecture

Universidad de Málaga (Spain) fjhormigo@uma.es

 New embedded applications increasingly

demanding FP computation

 IEEE-754 FP standard designed for GPP  Problems of using the FP standard: ▪ Lack of flexibility (Ex: word sizes) ▪ Compulsory requirements: costly and not always

useful (different rounding modes, special cases, subnormal…)

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 The problem exists:

▪ FPGA tools use almost compliant formats, but:

▪ Variable sizes, subnormals, special case flags… ▪ Special internal format (Intel fused FP-datapath)

▪ Synopsys Flexible Floating-Point format

▪ Two´s complement, flags, no normalization, truncation…

 Consequences:

▪ Multiple-variations of the standard are used=>

incompatibility and irreproducibility

▪ Hardware implementations less efficient

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Should a new extension of the FP standard be defined for embedded applications?

 Multiple choices could be re-studied for these new

applications: normalization, rounding, significand representation, special cases, etc.

 Here we focus on Normalization (and rounding)

▪ How normalization affects accuracy ▪ Implementation result improvement

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 Non-Normalized FP format  Proposed arithmetic circuits ▪ Adders ▪ Multipliers  Error measurement in DSP applications  Implementation results  Conclusions

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 Non-Normalized FP format  Proposed arithmetic circuits ▪ Adders ▪ Multipliers  Error measurement in DSP applications  Implementation results  Conclusions

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 Similar to binary32  Normalization is not compulsory  No special cases  Zero and subnormal are not special cases  Simplify rounding by using truncation: ▪ Round toward zero ▪ Round to nearest by using HUB approach [1]

[1] J. Hormigo and J. Villalba, “New formats for computing with real numbers under round-to-nearest”, IEEE Trans. on Computers, vol. 65, no. 7, pp. 2158–2168, 2016

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 If Normalization is not compulsory, it is lost:

• The implicit bit => 1 bit of precision
• Leading zeros => Accuracy
• Comparison operation
• Reproducibility

 But, it is improved:

+Area reduction +Power and energy reduction +Increase of the speed

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 If Normalization is not compulsory, it is lost:

• The implicit bit => 1 bit of precision
• Leading zeros => Accuracy
• Comparison operation
• Reproducibility

 But, it is improved:

+Area reduction +Power and energy reduction +Increase of the speed

Aproximate Computing (HW-accuracy trade-off)

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 Non-Normalized FP format  Proposed arithmetic circuits ▪ Adders ▪ Multipliers  Error measurement in DSP applications  Implementation results  Conclusions

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Basic FP Adder with no normalization(A1)

 No normalization or

rounding logic

 Only significand

• verflow is normalized

 Gray boxes => HUB

version

 Round-to-nearest

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FP Adder with limited normalization(A2)

 Up to two leading zero

detection and shifting

 Significand overflow is

also normalized

 Grey boxes => HUB

version

 Round-to-nearest

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WITHOUT SIGNIFICAND OVERFLOW DETECTION (M) WITH SIGNIFICAND OVERFLOW DETECTION (M2)

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 Leading zero detection at

the input

 LZz =LZx+LZy  Significand overflow is

always supposed

 Two versions:

▪ Limited (MLx) ▪ High radix (MRx)

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 Non-Normalized FP format  Proposed arithmetic circuits ▪ Adders ▪ Multipliers  Error measurement in DSP applications  Implementation results  Conclusions

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 Using non-normalized numbers implies a loss

• f accuracy

▪ Loss of the implicit leading one ▪ Unaligned addition ▪ Multiplications increase the number of leading

zeros

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 Using non-normalized numbers implies a loss

• f accuracy

▪ Loss of the implicit leading one ▪ Unaligned addition ▪ Multiplications increase the number of leading

zeros

1.0101011 .0101011

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 Using non-normalized numbers implies a loss

• f accuracy

▪ Loss of the implicit leading one ▪ Unaligned addition ▪ Multiplications increase the number of leading

zeros

1.1101101 + 0.0001011 1.0101011 .0101011

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 Using non-normalized numbers implies a loss

• f accuracy

▪ Loss of the implicit leading one ▪ Unaligned addition ▪ Multiplications increase the number of leading

zeros

1.1101101 + 0.0001011 0.0101011 0.1100111 00.010001011… x 1.0101011 .0101011

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 Experiment with several DSP algorithm

ARM A9 Non-Normalized Unit FP64 Error SNR FPGA A1MH

𝑇𝑂𝑆𝑒𝐶 = 10 ∗ 𝑚𝑝𝑕10 𝐹𝑧 𝐹𝑓𝑠𝑠𝑝𝑠

Reference Tested NoN architectures noN FP32

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A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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A2 A1 A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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IEEE HUB no HUB 146.2 A1 A2 A1 M 135.5 M2 133.8 135.9 124 MR1 133.9 135.5 123 MR4 132.0 135.5 123 MR8 1.3 135.5 1.3 ML4 133.9 135.5 123.4 ML6 133.9 135.5 123.2

A1: basic M: no ovf. MRx: radix-x norm. A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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 Round-to-nearest is essential  A2 is the best adder  A2M2H the best combination  Limited normalization in adders give better

accuracy than normalizing multipliers

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 Non-Normalized FP format  Proposed arithmetic circuits ▪ Adders ▪ Multipliers  Error measurement in DSP applications  Implementation results  Conclusions

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 Conditions: ▪ 32-bit FP architectures ▪ Fully combinational architectures ▪ Synopsys Design Compiler Ultra H-2013.03-SP2 ▪ TSMC 65nm Library typical case ▪ Area and power when targeting the same

frequency

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AREA POWER COMSUMPTION

• Very important reduction for all versions (around 40%-75%)
• Higher speed
• HUB version uses slightly less area and power
• Partial normalization has a significant cost

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AREA POWER COMSUMPTION

• Much less reduction than for adders
• Improvement comes from elimination of rounding logic
• HUB version slightly more area and power

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AREA POWER COMSUMPTION

A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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AREA POWER COMSUMPTION

A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm. Upper limit

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AREA POWER COMSUMPTION

A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm. Upper limit Lower limit

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AREA POWER COMSUMPTION

A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm.

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AREA POWER COMSUMPTION

A1: basic M: no ovf. MRx: radix-x norm. H: HUB A2: lim. norm. M2: ovf. MLx: lim. x-bit norm. About 25%- 50% Area and Power reduction

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 Non-Normalized FP format  Proposed arithmetic circuits ▪ Adders ▪ Multipliers  Error measurement in DSP applications  Implementation results  Conclusions

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 Removing normalization condition allows

hardware-cost vs accuracy trade-off

 Different adders and multipliers proposed for

dealing with this trade-off

 Rounding-to-nearest and a few-bit normalization

are enough to limit accuracy loss

 By reasonable loss of accuracy (10 dB), area and

power could be reduced up to 50%

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 Obtained results encourages us to continue by

seeking new non-normalized architectures, and testing more applications

 Other FP standard characteristics are also

questionable in embedded applications

 We aim for opening a debate about the need for

defining a new FP standard extension for new embeded applications

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Questions?