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Dependability and Security Challenges Dependability and Security - - PowerPoint PPT Presentation
Dependability and Security Challenges Dependability and Security - - PowerPoint PPT Presentation
Dependability and Security Challenges Dependability and Security Challenges in Emerging Technologies in Emerging Technologies Jacob A. Abraham Jacob A. Abraham University of Texas at Austin University of Texas at Austin Workshop Panel
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Process Variations
Source: Intel
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Nanoscale CMOS Example
Fin-FETs
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Effects on Circuits and Systems
Experiments on chips today show that running some chips at rated speeds produce errors
Correct operation when running at normal speeds
Resistive opens (possible in copper interconnect) cause delay defects Crosstalk effects could also cause errors As technology scales down, chips in the future prone to erroneous operation due to: Process variations (soft errors) Increasing defects (today's memories are an example)
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New Nano Systems
Carbon Nanotubes
Courtesy: IBM
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New Nano Systems
Inter-dot Barriers Outer Barriers Dot occupied by Electron Dot unoccupied 1 “1” “0” 1 QCA Wire 1 QCA Inverter Stable Unstable
Quantum Cellular Automata
Quantum Devices
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Dealing with Errors
Redundancy
Hardware (duplication/retry, triplication) Time (recomputation)
Basic ideas in dealing with errors are not new Moore and Shannon, 1956:
“Reliable Circuits Using Less Reliable Relays”
von Neumann, 1956:
“Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components”
Self-checking circuits (1970s) Algorithm-based fault tolerance (1980s) Software-based checks (control flow checks, etc.) (1980s)
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Redundancy at Different Levels
Switch (Circuit) level Module level
Voter
Functional Module
Checker
Outputs Error Inputs Self Checking System
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Protecting Computations at the System Level
Column Checksum Row Checksum ij
A Bjk
1 2 3 4 1 2 3 4
Algorithm-Based Fault Tolerance
Overhead decreases as system gets larger!
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CEDA: Control-flow Error Detection through Assertions (Integrated with GCC)
S: global runtime signature register – updated at the beginning and end of each node – each update either an XOR or an AND operation – op. performed based on the program graph properties
S = S XOR 1011 Se = 0011 Se = 1000 br S != 0011 err S = S XOR 0110 Se = 0101
Se: expected value of S at each point in the program
- calculated at compile time
Check point: S is checked against its expected value
- detects CFE if one occurred
- not required inside every node
Node signature: expected value of S inside a node Node exit signature: expected value of S immediately after exiting a node
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Dealing with Faults
Increasing possibility of defects Defect tolerance key for yield Want system to start in a good state
Cannot produce cost-effective DRAMS without replacing faulty cells with spares However, sparing cells is much more difficult for logic (very high cost for multiplexers, routing)
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Defect Tolerance in Carbon Nanotube Circuits
Source: Mitra
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What are some of the characteristics of future products?
Low-cost consumer products High frequency, high resolution signals System service (what matters is what customer sees) Regulations
200 400 600 800 1 000 1 200 1 400 19 91 '93 '95 '97 '99 20 01 '03 '05 '07 '09 '11
SoC Market Size World Wide Semiconducto r Market Size
MS-SOC Contribution to the SoC Market Size
Market Size (B$ ）
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Objective of dependability
Guarantee that the system meets customer or regulatory specifications Need not check directly for the specifications
This is becoming impossible to do with low cost
Only solution for systems of the future is indirect checks from which the specifications can be inferred accurately
Detector Output 10M Samples per Second
- 2.5
- 2
- 1.5
- 1
- 0.5
0.5 1 1.5
- 2.5
- 2
- 1.5
- 1
- 0.5
0.5 1 1.5 Predicted IIP3 [dBm] Measured IIP3 [dBm] LNA IIP3 IIP3 y=x ref line
Third harmonic of 940 MHz RF system deduced from 10 MS/sec detector output
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