DEC1622 Team Leader : Wei Shen Theh Communication Leader : Jiayu - - PowerPoint PPT Presentation

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DEC1622 Team Leader : Wei Shen Theh Communication Leader : Jiayu - - PowerPoint PPT Presentation

Fast, Compact, High Strength Magnetic Field Generator DEC1622 Team Leader : Wei Shen Theh Communication Leader : Jiayu Hong Key Concept Holder : Aqila Sarah Zulkifli Webmaster : Wing Yi Lwe Advisor: Dr. Mani Mina Co-advisors: Neelam Prabhu


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Fast, Compact, High Strength Magnetic Field Generator

Team Leader : Wei Shen Theh Communication Leader : Jiayu Hong Key Concept Holder : Aqila Sarah Zulkifli Webmaster : Wing Yi Lwe Advisor: Dr. Mani Mina Co-advisors: Neelam Prabhu Gaunkar, : Jayaprakash Selvaraj Client : Iowa State University’s High Speed System Engineering Lab

DEC1622

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Presentation Outline

1. Objective 2. Applications 3. Project Flow 4. Circuit Block Diagram 5. Schematic Diagram 6. Design Process a. FET Options b. Coil Size

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Objective

  • Design and fabricate a high-speed magnetic field generation circuit

Requirements

  • High magnetic flux density (500 Gauss)
  • Rise time (<100ns)
  • Footprint 2” x 2”

Our focus

  • Current
  • Switching speeds

Purpose Design Objective

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Possible Applications

Source: New developments in magneto-optic interferometric switching by John Pritchard

  • 1. Magneto-Optic Switch

Figure: Sagnac Interferometer

MO Material

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Possible Applications

  • 2. Fiber-Optic Networking Systems

Source: New developments in magneto-optic interferometric switching by John Pritchard

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Project Flow

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Circuit Block Diagram

When MOSFET is turned off, DC source charges capacitors Pulse is fed to control the switching

  • f the MOSFET

Capacitor releases stored energy to inductor coil Output current is measured through current sense resistor When MOSFET is turned

  • ff, charges stored in

inductive coil is dissipated as heat through resistor Diode ensure current does not pass through discharge resistor when switch is on 1 3 2 7 6 Inductor coil generates magnetic field 5 4

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Schematic Diagram

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Switch options: MOSFET Darlington Considerations: MOSFET - Faster switch Darlington - BJT based

Design Process

BJT - NPN Darlington structure NMOS

Source: ibiblio.org Source: thinkelectronics Source: keysight

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Comparison MOSFET & BJT

L=200pH Improved rise time makes MOSFET our favored switch!

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Input Capacitance: PSMN4R0-30YLD (1272 pF) CSD17322Q5A (580 pF) IRL3714S (670 pF) PSMN1R2-30YLD (4616 pF) Time Constant:

MOSFET's Input Capacitance

D S Cgd Cgs Cds

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Coil Size

102nH: length:0.6cm,radius:0.25cm, turns:5 78nH: length:0.5cm,radius:0.20cm, turns:5

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Testing

  • Vdc = 15V
  • Pulse width = 1us
  • Period = 10ms
  • V+ = 5V
  • V- = 0V
  • Rise time reference level

○ 10% - 90% ○ 20% - 80% Two Inductors: 102nH & 78nH Two different set of input: 1us & 2us

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Design Analysis: Previous Design

Source: http://may1530.ece.iastate.edu/

500 Gauss 1 us 2” x 1.5”

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Challenges

Importing footprints and SPICE files Tiny components Protomat has limiting functions:

Single layer No plated through hole

No experience with:

Eagle layout Protomat

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Footprint: 1.5” x 1.875”

  • Chosen NXP PSMN1R2-30YLD without realizing

huge input capacitance (4616 pF)

  • Does not work

○ Positive DC input is not connected to the rest of the circuit

Layout 1 (PSMN1R2-30YLD)

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Layout 2 (PSMN1R2-30YLD)

Footprint: 2.2” x 1.95”

Inductance 102 nH 78.5 nH Rise time (10% - 90%) 744 ns 664 ns Rise time (20% - 80%) 612 ns 504 ns Mean voltage 0.64 V 0.68 V Max voltage 0.8 V 0.84 V Magnetic flux density 167.5 G 157.93 G

First working board! Same NXP MOSFET Low magnetic flux density (167 Gauss) Slower rise time (>100ns) Relatively large footprint (within 2’’x 2’’)

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TI CSD17322Q5A with low input capacitance (580 pF) Shorter rise time (9x faster) Board performing as expected

Layout 3 (CSD17322Q5A)

Inductance 102 nH 78.5 nH Rise time (10% - 90%) 83.200 ns 129.967 ns Rise time (20% - 80%) 58.467 ns 94.313 ns Mean voltage 1.640 V 2.027 V Max voltage 1.640 V 1.947 V Magnetic flux density 343.481 G 407.709 G

Footprint: 1.8” x 1.4”

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Without zener protection circuit Decreased magnetic flux density (20G) Rise time further decreases (26 ns) Ground terminals positioned closer Spiking and oscillation improved Board size decrease

Layout 4 (CSD17322Q5A w/o Zener)

Inductance 102 nH 78.5 nH Rise time (10% - 90%) 56.990 ns 86.297 ns Rise time (20% - 80%) 31.530 ns 54.507 ns Mean voltage 1.527 V 1.527 V Max voltage 1.540 V 1.567 V Magnetic flux density 322.537 G 328.122 G

Footprint: 1.5” x 1.1”

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Layout 5 (IRL3714S w/o Zener)

Inductance 102 nH 78.5 nH Rise time (10% - 90%) 60.690 ns 69.850 ns Rise time (20% - 80%) 39.480 ns 48.177 ns Mean voltage 1.24 V 1.23 V Max voltage 1.36 V 1.23 V Magnetic flux density 284.838 G 258.309 G

Footprint: 1.5” x 1.25”

Without zener protection circuit IRF IRL3714S (670 pF input capacitance) Low magnetic flux density and short rise time Ground terminals routed together

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Final Board

Based on layout design 3 NXP PSMN4R0-30YLD (1272 pF input capacitance) Industry PCB and reflow oven soldering Inductor coil soldered onto board

Inductance 102 nH Rise time (10% - 90%) 111.45 ns Rise time (20% - 80%) 75.635 ns Mean voltage 2.08 V Max voltage 2.08 V Magnetic flux density 435.63 G

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Conclusion

Final Board Project Specification Previous Work Rise time 111.45 ns 100 ns ~500 ns Magnetic flux density 435.63 G 500 G 500 G Footprint 1.8” x 1.4” 2” x 2” 2” x 1.5” Cost per board(approx) $28

  • $30
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Questions?

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Appendix

Layout 2 Layout 3 Layout 4 Layout 5 102nH 78nH

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Thank You!