DEC1622 Team Leader : Wei Shen Theh Communication Leader : Jiayu - PowerPoint PPT Presentation

Fast, Compact, High Strength Magnetic Field Generator DEC1622 Team Leader : Wei Shen Theh Communication Leader : Jiayu Hong Key Concept Holder : Aqila Sarah Zulkifli Webmaster : Wing Yi Lwe Advisor: Dr. Mani Mina Co-advisors: Neelam Prabhu Gaunkar, : Jayaprakash Selvaraj Client : Iowa State University’s High Speed System Engineering Lab dec1622@iastate.edu

Presentation Outline 1. Objective 2. Applications 3. Project Flow 4. Circuit Block Diagram 5. Schematic Diagram 6. Design Process a. FET Options dec1622@iastate.edu b. Coil Size

Design Objective Purpose Objective ● Design and fabricate a high-speed magnetic field generation circuit Requirements ● High magnetic flux density (500 Gauss) ● Rise time (<100ns) ● Footprint 2” x 2” Our focus ● Current ● Switching speeds dec1622@iastate.edu

Possible Applications 1. Magneto-Optic Switch MO Material Figure: Sagnac Interferometer dec1622@iastate.edu Source: New developments in magneto-optic interferometric switching by John Pritchard

Possible Applications 2. Fiber-Optic Networking Systems dec1622@iastate.edu Source: New developments in magneto-optic interferometric switching by John Pritchard

Project Flow dec1622@iastate.edu

Circuit Block Diagram Capacitor releases stored energy to inductor coil 4 Inductor coil When MOSFET is generates turned off, DC source magnetic field charges capacitors Diode ensure current 5 does not pass through 1 discharge resistor when switch is on 3 When MOSFET is turned off, charges stored in inductive coil is dissipated as heat through resistor 7 Output current is Pulse is fed to measured through control the switching current sense of the MOSFET resistor 2 6 dec1622@iastate.edu

Schematic Diagram dec1622@iastate.edu

Design Process Switch options: MOSFET Darlington Source: thinkelectronics Source: keysight Considerations: BJT - NPN NMOS MOSFET - Faster switch Darlington - BJT based Darlington structure Source: ibiblio.org dec1622@iastate.edu

Comparison MOSFET & BJT L=200pH Improved rise time makes MOSFET our favored switch! dec1622@iastate.edu

MOSFET's Input Capacitance Input Capacitance: PSMN4R0-30YLD (1272 pF) Cds CSD17322Q5A (580 pF) Cgd D IRL3714S (670 pF) S Cgs PSMN1R2-30YLD (4616 pF) Time Constant: dec1622@iastate.edu

Coil Size 102nH: length:0.6cm,radius:0.25cm, turns:5 78nH: length:0.5cm,radius:0.20cm, turns:5 dec1622@iastate.edu

Testing ● Vdc = 15V ● Pulse width = 1us ● Period = 10ms ● V+ = 5V ● V- = 0V ● Rise time reference level ○ 10% - 90% ○ 20% - 80% Two Inductors: 102nH & 78nH dec1622@iastate.edu Two different set of input: 1us & 2us

Design Analysis: Previous Design 500 Gauss 1 us 2” x 1.5” dec1622@iastate.edu Source: http://may1530.ece.iastate.edu/

Challenges Importing footprints and SPICE files Tiny components Protomat has limiting functions: Single layer No plated through hole No experience with: Eagle layout dec1622@iastate.edu Protomat

Layout 1 (PSMN1R2-30YLD) Footprint: 1.5” x 1.875” ● Chosen NXP PSMN1R2-30YLD without realizing huge input capacitance (4616 pF) ● Does not work ○ Positive DC input is not connected to the rest of the circuit dec1622@iastate.edu

Layout 2 (PSMN1R2-30YLD) Footprint: 2.2” x 1.95” 102 nH 78.5 nH Inductance 664 ns Rise time 744 ns (10% - 90%) Rise time 612 ns 504 ns First working board! (20% - 80%) Mean voltage 0.64 V 0.68 V Same NXP MOSFET Max voltage 0.8 V 0.84 V Low magnetic flux density (167 Gauss) 157.93 G Magnetic flux 167.5 G density Slower rise time (>100ns) Relatively large footprint (within 2’’x 2’’) dec1622@iastate.edu

Layout 3 (CSD17322Q5A) Footprint: 1.8” x 1.4” Inductance 102 nH 78.5 nH Rise time 83.200 ns 129.967 ns (10% - 90%) Rise time 58.467 ns 94.313 ns (20% - 80%) Mean voltage 1.640 V 2.027 V TI CSD17322Q5A with low input capacitance (580 Max voltage 1.640 V 1.947 V pF) Magnetic flux 343.481 G 407.709 G Shorter rise time (9x faster) density Board performing as expected dec1622@iastate.edu

Layout 4 (CSD17322Q5A w/o Zener) Footprint: 1.5” x 1.1” Inductance 102 nH 78.5 nH 86.297 ns Rise time 56.990 ns (10% - 90%) Rise time 31.530 ns 54.507 ns (20% - 80%) Without zener protection circuit Mean 1.527 V 1.527 V voltage Decreased magnetic flux density (20G) Rise time further decreases (26 ns) Max voltage 1.540 V 1.567 V Ground terminals positioned closer 328.122 G Magnetic 322.537 G Spiking and oscillation improved flux density Board size decrease dec1622@iastate.edu

Layout 5 (IRL3714S w/o Zener) Footprint: 1.5” x 1.25” Inductance 102 nH 78.5 nH 69.850 ns Rise time 60.690 ns (10% - 90%) 39.480 ns 48.177 ns Rise time (20% - 80%) Mean voltage 1.24 V 1.23 V Without zener protection circuit 1.36 V 1.23 V Max voltage IRF IRL3714S (670 pF input capacitance) Magnetic flux 284.838 G 258.309 G density Low magnetic flux density and short rise time dec1622@iastate.edu Ground terminals routed together

Final Board Inductance 102 nH Rise time 111.45 ns (10% - 90%) 75.635 ns Rise time (20% - 80%) Mean voltage 2.08 V Based on layout design 3 2.08 V Max voltage NXP PSMN4R0-30YLD (1272 pF input capacitance) Magnetic flux 435.63 G Industry PCB and reflow oven soldering density dec1622@iastate.edu Inductor coil soldered onto board

Conclusion Final Board Project Specification Previous Work Rise time 111.45 ns 100 ns ~500 ns Magnetic flux density 435.63 G 500 G 500 G 1.8” x 1.4” 2” x 2” 2” x 1.5” Footprint Cost per $28 - $30 board(approx) dec1622@iastate.edu

Questions? dec1622@iastate.edu

Appendix Layout 3 102nH Layout 2 78nH Layout 4 Layout 5 dec1622@iastate.edu

Thank You!