Introduction to AXI – Custom IP C r i s t i a n S i s t e r n a U n i v e r s i d a d N a c i o n a l d e S a n J u a n A r g e n t i n a
Agenda ◦ Describe the AXI4 transactions ◦ Summarize the AXI4 valid/ready acknowledgment model ◦ Discuss the AXI4 transactional modes of overlap and simultaneous operations ◦ Describe the operation of the AXI4 streaming protocol AXI - Custom IP ICTP - IAEA
Need to Understand Device’s Connectivity • There is a need to get familiar with the way that different devices communicate each other in an Embedded System like a Zynq based system • Learning and understanding the communication among devices will facilitate the design of Zynq based systems • All the devices in a Zynq system communicate each other based in a device interface standard developed by ARM, called AXI (ARM eXtended Interface): • AXI define a Point to Point Master/Slave Interface AXI - Custom IP ICTP - IAEA 3
Today’s System -On On-Chip General Purpose CPU DDR Controller I/O Shared DRAM Memory Vide Controller SPI Ethernet DAC Controller USB ADC AXI - Custom IP ICTP - IAEA 4
Interface Options PLBv46 – Bus Spec PLB Processor S_AXI M_AXI S_AXI M_AXI P1 Processor S_AXI M_AXI P1 PLB M_AXI S_AXI AXI P2 Inteconnect P2 PLB S_AXI M_AXI P3 P3 AXI4 Defines a PLB Point to Point Master/Slave Arbiter Peripherals Interface ICTP - IAEA 5 AXI - Custom IP
Connectivity -> Standard • A standard • All units talk based on the same standard (same protocol, same language) • All units can easily talk to each other • Maintanence • Design is easily maintined/updated • Facilitate debug tasks • Re-Use • Developed cores can easily re-used in other systems AXI - Custom IP ICTP - IAEA 6
Common SoC Interfaces • Core Connect (IBM) • PLB/OPB (Power PC-FPGA bus interface) • WishBone • OpenCore Cores • AXI • ARM standard (more to come . . . ) AXI - Custom IP ICTP - IAEA 7
AXI is Part of ARM’s AMBA AMBA AMBA 3.0 AXI APB AHB (2003) Performance Newer Older AMBA: Advanced Microcontroller Bus Architecture AXI: Advanced Extensible Interface 8 AXI - Custom IP ICTP - IAEA
AXI is Part of AMBA AMBA Enhancements for FPGAs APB AHB AXI ATB AMBA 3.0 (2003) Same Spec AXI-4 AXI-4 AXI-4 AMBA 4.0 Memory Map Stream Lite (2010) Interface Features Burst Data Width Applications Traditional Address/Data Burst Embedded, AXI4 Up to 256 32 to 1024 bits Memory (single address, multiple data) DSP, Video, AXI4-Stream Data-Only, Burst Unlimited Any Number Communications Traditional Address/Data — No Burst (single Small Control AXI4-Lite 1 32 or 64 bits address, single data) Logic, FSM 9 AXI - Custom IP ICTP - IAEA
AXI – Vocabulary Channel ◦ Independent collection of AXI signals associated to a VALID signal Interface ◦ Collection or more channles that expose an IP core’s connectin a master to a slave ◦ Each IP core may have multiple interfaces Bus ◦ Multiple-bit signal (not an interface or channel) Transfer ◦ Single clock cycle where information is communicated, qualified by a a VALID handshake Transaction ◦ Complete communication operation across a channel, composed of a one or more transfers Burst ◦ Transaction that consists of more than one transfer ICTP - IAEA 10 AXI - Custom IP
AXI Transactions / Master-Slave Responds to the Initiates the Write Transaction initiate transaction transaction AXI AXI Slave Master Read Transaction Transactions: transfer of data from one point on the hardware to another point ICTP - IAEA 11 AXI - Custom IP
More than One-to to-One AXI AXI Slave Master ? ? AXI AXI Slave Master AXI Master AXI Slave ICTP - IAEA 12 AXI - Custom IP
AXI Interconnect AXI is an interconnect system used to tie processors to peripherals ◦ AXI Full memory map: Full performance bursting interconnect ◦ AXI Lite: Lower performance non bursting interconnect (saves programmable logic resources) ◦ AXI Streaming: Non-addressed packet based or raw interface 13 AXI - Custom IP ICTP - IAEA
AXI Interconnect AXI Slave M_AXI S_AXI SPI AXI M_AXI S_AXI Master CPU ? AXI AXI Master Interconnect DMA M_AXI S_AXI S_AXI M_AXI AXI Slave GPIO S_AXI M_AXI AXI Slave BRAM AXI - Custom IP ICTP - IAEA 14
AXI Interconnect – Addressing & Decoding Address Decoding Table GPIO: 0X4000_0000 SPI: 0X4000_1000 BRAM: 0X4001_0000 Address Range : 4K Address Offset : 0X4000_1000 Addresses : 0X4000_0000 – 0X4000_1FFF Address Range : 4K Address Offset : 0X4000_0000 Address Range : 64K Addresses : 0X4000_0000 – 0X4000_0FFF Address Offset : 0X4001_0000 Addresses : 0X4001_0000 – 0X4001_FFFF AXI - Custom IP ICTP - IAEA 15
AXI Interconnect Main Features • Different Number of (up to 16) • Slave Ports • Master Ports • Data Width Conversion • Conversion from AXI3 to AXI4 • Register Slices, Input/Output FIFOs • Clock Domains Transfer AXI - Custom IP ICTP - IAEA 16
AXI Interconnect axi_interconnect component o ◦ Highly configurable ◦ Pass Through ◦ Conversion Only ◦ N-to-1 Interconnect ◦ 1-to-N Interconnect ◦ N-to-M Interconnect – full crossbar ◦ N-to-M Interconnect – shared bus structure Decoupled master and slave interfaces o o Xilinx provides three configurable ◦ AXI4 Lite Slave ◦ AXI4 Lite Master ◦ AXI4 Slave Burst Xilinx AXI Reference Guide(UG761) o AXI - Custom IP ICTP - IAEA
AXI Interface Example ICTP - IAEA 18 AXI - Custom IP
AXI Interface Example ICTP - IAEA 19 AXI - Custom IP
AXI Slave Signals ICTP - IAEA 20 AXI - Custom IP
Basic AXI Rd/Wr Process ICTP - IAEA 21 AXI - Custom IP
AXI Channels Use A Basic “VALID/READY” Handshake Master asserts and hold VALID when data is available 1 Slave asserts READY if able to accept data DATA 2 AXI AXI VALID 3 Data and other signals transferred when VALID and READY = ‘1’ Slave Master READY Master sends next DATA/other signals or deasserts VALID 4 ACLK Slave deasserts READY if no longer able to accept data 5 3 3 3 3 4 4 1 1 5 5 5 2 2 2 22 AXI - Custom IP ICTP - IAEA
AXI Channels (AXI4 and AXI Lite) Read Address Channel Address and Control AXI4 AXI4 AXI4 Read Master Slave Read Data Channel Read Read Read Read Data Data Data Data Write Address Channel Address and Control Write Data Channel AXI4 Write Write Write Write AXI4 AXI4 Write Data Data Data Data Master Slave Write Response Channel Write Response AXI - Custom IP ICTP - IAEA 23
AXI Slave - Channels ICTP - IAEA 24 AXI - Custom IP
(Full) AXI4 Read Address Channel Address and Control AXI AXI Master Slave Read Data Channel o Sometimes called “ Full AXI ” Read Read Read Read or “ AXI Memory Mapped ” Data Data Data Data o Single address multiple data o Burst up to 256 data Write Address Channel Address and o Data Width parameterizable Control o 32, 64, 128, 256, 512, 1024 Write Data Channel bits AXI Write Write Write Write AXI Data Data Data Data Master Slave Write Response Channel Write Response AXI - Custom IP ICTP - IAEA 25
AXI4 Stream o No address channel, no read and write, always just Master to Slave Write Data Channel o Just an AXI4 Write Channel AXI Write Write Write Write AXI Data Data Data Data Master Slave o Unlimited burst length o Supports sparse, continuous, aligned, unaligned streams AXI - Custom IP ICTP - IAEA 26
AXI Stream Data Data Master Slave Slave AXI AXI AXI AXIS_M AXIS_S AXIS_S AXI - Custom IP ICTP - IAEA 27
AXI4 Lite Read Address Channel Address and Control AXI AXI o No Burst Master Slave Read Data Channel Read Read o Single address, single data Read Read Data Data Data Data o Data Width 32 or 64 bits (Xilinx IP only support 32) Write Address Channel o Very small size Address and Control o The AXI Interconnect is Write Data Channel automatically generated AXI Write Write Write Write AXI Data Data Data Data Master Slave Write Response Channel Write Response AXI - Custom IP ICTP - IAEA 28
AXI4 Lite Read Read Address Channel Address and Control AXI AXI Master Slave Read Data Channel Read Read Read Read Data Data Data Data AXI - Custom IP ICTP - IAEA 29
AXI4 Lite Write Write Address Channel Address and Control Write Data Channel AXI Write Write Write Write AXI Data Data Data Data Master Slave Write Response Channel Write Response AXI - Custom IP ICTP - IAEA 30
AXI4 – AXI Lite: Signals Available AXI - Custom IP ICTP - IAEA 31
AXI4-Lite Custom IP The VHDL Underneath AXI - Custom IP ICTP - IAEA 32
AXI4-Lite Signal Names ICTP - IAEA 33 AXI - Custom IP
AXI4-Lite Signal Names o During the creation of a Xilinx IP block, the Vivado tools can be used to map each AXI signal onto the signal name that the designer used when creating the IP o However in order to make the life of the designer much easier, the signal names shown here are recommended when designing a custom AXI slave in VHDL o Using these signal names will allow the Vivado design tools to automatically detect the signal names during the “create and package IP” step (described later on). ICTP - IAEA 34 AXI - Custom IP
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