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Automated Placement for Custom Digital Designs Tung-Chieh Chen - - PowerPoint PPT Presentation
Automated Placement for Custom Digital Designs Tung-Chieh Chen - - PowerPoint PPT Presentation
Automated Placement for Custom Digital Designs Tung-Chieh Chen Physical Design Group, SpringSoft Inc. Mar 29 2011 (ISPD-2011) Outline Why Placement Custom Summary Issues Digital ISPD-2011 1 Outline Why Placement Custom Summary
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Outline
Why Custom Digital Placement Issues Summary
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Why Custom Digital
Allow precise custom design of digital blocks
- ften used in mixed-signal environment
Meet the critical performance requirements that
- ften cannot be achieved by standard digital
design flow
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Properties for Custom Digital Designs
Tight Utilization Limited Metal Layers Various Placement Constraints
Need unique automation techniques to solve issues in custom digital placement
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Placement Issues
Area Routability Constraints
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Outline
Why Custom Digital Placement Issues Summary
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Placement Issues
Area Routability Constraints
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Area Minimization
How to minimize placement area?
- Reduce whitespace by increasing cell
utilization
- Overlap cells
Cell overlapping by oxide diffusion sharing
- A common technique used in transistor-level
placement but not in cell-level placement
- Cells with common power/ground portion can
be overlapped to reduce area
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Cell Overlapping Example
Abutting Overlapping Overlapped Region
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Input
- A cell placement
- A list of allowable cell overlap combinations
- For example, INV-Right and INV-Right means an
INV (R0) can be overlapped with an INV (MirrorY)
Decide the new orientation of each cell so that the number of cell overlaps for adjacent cells can be maximized
Cell Overlapping Problem
INV R0 INV MY
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Cell Overlapping Study
Cell # CellArea / RowArea Reduced Area Without
- verlapping
With Overlapping Case1 85 99.9% 106.7% 6.8% Case2 87 95.1% 106.3% 11.8% Case3 113 98.1% 110.8% 13.0% Case4 362 99.6% 106.1% 6.5%
1p3m Area reduction is around 6% to 13%
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Problem of Squeezing Cells…
Routability
- Need a better routing plan (topology) to
utilize the routing resources Electrostatic discharge (ESD) path
- Prevent a direct power-to-ground current path
with small resistance
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Electrostatic Discharge (ESD) Path
Direct connection of power-to-ground rails without tie cells can be used to compact size in a high utilization design A larger spacing rule is used to avoid direct power ground path due to small resistance
VDD GND
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Solving ESD Spacing Rule
VDD GND Need larger spacing to increase resistance from power to ground Increase cell spacing to prevent the violation Flip the cell to reduce cell spacing while keeping the same ESD space rule
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ESD-Violation-Fixing Problem
Input
- A cell placement
- ESD spacing rule
- Direct tie-high/low pins
Decide new cell positions and orientations so that all ESD spacing violations are resolved and the change of cell positions and orientations are minimized
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Placement Issues
Area Routability Constraints
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Improving Routability
Spine Routing Topology
- More predictable for resource usage, wire
length, source-to-sink path, etc.
Spine
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Floorplan for Spine Routing
Channels are pre-defined before cell placement Pro: * Channel sizes can be different Channels are automatically created during placement Pro: * No need to define channels before placement * Cell positions are more flexible Channel Floorplan Pseudo-Channel Floorplan
Spine Nets
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Need an Accurate Net Model for Spine Nets
A pin is usually modeled by using a point NOT accurate for a large pin (spine)
The desired cell moving directions Using an inaccurate net model for a spine net may cause cells collapsed to a point
Spine net Spine net
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Complex Spine Topology
Placement becomes harder when spine topology becomes complicated
Main Spine Secondary Spine
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F.-Y. Chang et al., “Cut-Demand Based Routing Resource Allocation and Consolidation for Routability Enhancement,” ASP-DAC 2010 How to create “useful routing tracks”?
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Pseudo-Channel Placement
“useful routing tracks” “useless routing tracks”
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Wire Length vs. Routing Track Number
Routing track may not be reduced when minimizing wire length
A D B E C A B C D E Net1 Net2 Net3 Net1 Net2 Net3 Wirelength = 8 Track = 3 Wirelength = 8 Track = 2
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Placement Issues
Area Routability Constraints
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Placement Constraints
Symmetry constraints Relative placement constraints Hierarchy constraint All constraints should be followed at any stage
- f automatic placement
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Symmetry Constraint
Symmetric placement for device/net matching
symmetry placement about x-axis
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Relative Placement Constraint
Also known as structure/matrix placement Good for data-path designs Constraints can be defined in a matrix style (col/row)
Row 1 Row 2 Row 3 Row 4 Row 5 Row 6
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Hierarchy Constraint
Placement while keeping cells in the same hierarchy block No overlap between cells in different hierarchy blocks (cellviews)
A B C TOP block level cell level
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Outline
Why Custom Digital Placement Issues Summary
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Summary
- Cell overlapping
- ESD rule spacing
Area
- Spine routing topology
- Pseudo-channel floorplan
- Track number vs. wire length
Routability
- Symmetry
- Relative placement
- Hierarchy
Constraints
Issues in automated custom digital placement
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