CS 251 Fall 2019 CS 240 Principles of Programming Languages - - PowerPoint PPT Presentation
CS 251 Fall 2019 CS 240 Principles of Programming Languages Foundations of Computer Systems Ben Wood Sequential Logic Latch: CC-BY Rberteig@flickr and State Output depends on inputs and stored values . (vs. combinational logic: output
CS 251 Fall 2019 Principles of Programming Languages
Ben Wood
CS 240
Foundations of Computer Systems
https://cs.wellesley.edu/~cs240/
Output depends on inputs and stored values. (vs. combinational logic: output depends only on inputs) Elements to store values: latches, flip-flops, registers, memory
Sequential Logic 1
Latch: CC-BY Rberteig@flickr
Sequential Logic 2
Registers Memory
Instruction Fetch and Decode
Sequential Logic 3
Q Q
Suppose we somehow get a 1 (or a 0?) on here.
Q Q
Sequential Logic 4
Q Q R S Set Reset S R Q Q' Q (stable) Q' (stable) 1 1 1 1 1 ? ? 1 1 ? ? 1
Sequential Logic 5
Q Q R S Q Q R S Q Q R S R S Q Q R S Q Q
if C = 0, then SR latch stores current value of Q. if C = 1, then D flows to Q: if D = 0, then R = 1 and S = 0, Q = 0 if D = 1, then R = 0 and S = 1, Q = 1
Sequential Logic 6
D C R S Q Q Clock Data bit
Sequential Logic 7
D C Q
Assume Q has an initial state of 0
Clock: free-running signal with fixed cycle time = clock period = T. Clock frequency = 1 / clock period A clock controls when to update a sequential logic element's state.
Sequential Logic 8
Clock period Falling edge Rising edge
Inputs to state elements must be valid on active clock edge.
Sequential Logic 9
State element 1 State element 2 Combinational logic
Sequential Logic 10
QL DL CL
D latch
QL QF DF CF
D latch
QF
Clock
leader stores D as E follower stores E as Q Can still read Qnow Qnext becomes Qnow
Time
Sequential Logic 11
D C E Q
Assume Q and E have an initial state of 0
Sequential Logic 12
Assume Q is initially 0.
Q D C D Flip-Flop Q Clock
Sequential Logic 13
Q D C D Flip-Flop Q 1
(a 4-bit hardware storage cell)
Sequential Logic 14
Write Clock
1 1 Q D C D Flip-Flop Q Q D C D Flip-Flop Q Q D C D Flip-Flop Q Q D C D Flip-Flop Q
*Half a byte!
Sequential Logic 15
Read ports Why 2?
Read register selector 1 Read register selector 2 Write register selector Write data Write? Read data 1 Read data 2
r r r w w w
r = log2 number of registers w = bits in word
Array of registers, with register selectors, write/read control, input port for writing data, output ports for reading data. Write port
0 = read 1 = write
Sequential Logic 16
Read register number 1 Register 0 Register 1 . . . Register n – 2 Register n – 1 M u x Read register number 2 M u x Read data 1 Read data 2
Write 1 n-to-2n decoder n – 2 n – 1 Register 0 C D Register 1 C D Register n – 2 C D Register n – 1 C D . . . Register number . . . Register data
Sequential Logic 17
incoming data register number write control clock
Sequential Logic 18
Similar to register file, except… A B
Sequential Logic 19
4 to 16 decoder data
1101
4-bit address