CREATING, ACQUIRING AND INTEGRATING REUSABLE IP Prof. Don Bouldin, - - PowerPoint PPT Presentation

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CREATING, ACQUIRING AND INTEGRATING REUSABLE IP Prof. Don Bouldin, - - PowerPoint PPT Presentation

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CREATING, ACQUIRING AND INTEGRATING REUSABLE IP Prof. Don Bouldin, Ph.D. Electrical & Computer Engineering University of Tennessee Knoxville, TN 37996-2100 dbouldin@tennessee.edu IEEE Boston 14 November 2007

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CREATING, ACQUIRING AND INTEGRATING REUSABLE IP

  • Prof. Don Bouldin, Ph.D.

Electrical & Computer Engineering University of Tennessee Knoxville, TN 37996-2100 dbouldin@tennessee.edu IEEE Boston 14 November 2007 http://vlsi1.engr.utk.edu/~bouldin/boston

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OUTLINE OF THIS PRESENTATION

  • Design Productivity
  • Intellectual Property Blocks
  • Reuse Requirements
  • The Changing Design Environment
  • Acquiring IP Blocks
  • Quality IP Metrics
  • Collaborative Design
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ELECTRONIC PRODUCTS ARE PERVASIVE AND ALWAYS IMPROVING

Price Price Performance Performance $1000--1X $1000--1X $500--1X $500--1X $1000--2X $1000--2X

Moore’s Law: Every 18 months integrated circuit manufacturing can produce 2X performance for the same price or the same performance for half the price. Moore’s Law: Every 18 months integrated circuit manufacturing can produce 2X performance for the same price or the same performance for half the price.

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10,000,000

Logic Transistors per Chip (K) Productivity Trans./Staff-Mo.

The Impending Design Productivity Crisis

1,000,000 100,000 10,000 1,000 100 10 1 100,000,000 10,000,000 1,000,000 100,000 10,000 1,000 100 10 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009

58%/Yr. Compounded Complexity growth rate 21%/Yr. Compounded Productivity growth rate Source: SEMATECH x x x xx x x Logic Tr./Chip Tr./S.M.

A DESIGN PRODUCTIVITY CRISIS WAS PREDICTED A DECADE AGO

Maya Rubeiz USAF Wright Labs maya.rubeiz@sn.wpafb.af.mil http://rassp.scra.org 1997

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DESIGN PRODUCTIVITY HAS PROGRESSED RECENTLY

  • 1947
  • 3 Nobel Laureates
  • 1 Transistor
  • 2007
  • 3 ECE Students
  • 4M Transistors

Progress has been enabled by raising the level of abstraction and reusing previous sub-systems or blocks.

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WE BUILD SKYSCRAPERS USING STANDARDIZED BLOCKS

So, let’s use standardized blocks Sears Tower, Chicago Sears Tower, Chicago to build systems www.lego.com www.lego.com

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INTELLECTUAL PROPERTY BLOCKS

IP blocks should have well-defined interfaces Often, IP are more like patches that must be stitched together like a quilt

Design #1 without Planned Reuse Design #2 without Planned Reuse Design #3 without Planned Reuse Design # 1 For Reuse 1.5

Design #2 WITH IP

1.8

Design #3 WITH IP

2.1

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IP IS CREATED USING A HARDWARE DESCRIPTION LANGUAGE OR HDL

CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ;

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AN HDL DESIGN CAN BE TARGETED TO MULTIPLE LAYOUTS

SCHEMATIC--A AND OR AND HDL

architecture behavior of control is if left_paddle then n_state <= hit_state elsif n_state <= miss_state end if;

SYNTHESIS PHYSICAL LAYOUT ALTERA PLACE & ROUTE SCHEMATIC--B AND OR PHYSICAL LAYOUT LIBRARIES OR TECH A TECH B TECH A TECH B SYNPLIFY_PRO SYNPLIFY_PRO XILINX PLACE & ROUTE

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  • BASICS:

– HDL Models – Functional Description – Application Intent – Interface Specifications – Authors and Owners – Size, Delay, Power Estimates – Packaging Info

REQUIREMENTS FOR REUSABLE IP

  • ALSO NEED:

– Test Bench (Input Stimuli/Output Responses – Tools and Versions Used/Needed – Foundry Used For Fab – Size, Delay, Power Measurements – Testability Features (BIST, JTAG, SCAN)

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THE DESIGN METHOD HAS CHANGED

1. Select ICs 2. Design/Fab PCB 3. Design blocks for new IC 4. Integrate blocks 5. System Integration 1. Select PCB with ICs 2. Select blocks for new IC 3. Design missing blocks 4. Integrate blocks 5. System Integration

CUSTOMER Requirements DESIGNER Specifications

OLD METHOD OLD METHOD NEW METHOD NEW METHOD

UNCHANGED UNCHANGED

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IP CAN ATTRACT BUSINESS AND REDUCE RISK AND TIME-TO-MARKET

CUSTOMER Foundry Design Center IP IP ASIC/FPGA

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AN OPEN COMPETITIVE MARKET EXISTS

REPOSITORY www.design-reuse.com CUSTOMER PORTABLE IP (Multiple Suppliers) Standards: www.vsia.org www.ieee.org Foundry ASIC/FPGA Foundry Foundry

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  • LEON is an open-source 32-bit

SPARC V8 CPU that was developed by the European Space Agency and is available for free at www.gaisler.com

FREE OPEN-SOURCE CORES

  • Other cores at www.opencores.org

–USB 2.0 –Ethernet MAC –DES/AES Encryption –FIR/IIR Filters –Floating Point Unit

  • Other cores at www.opencores.org

–USB 2.0 –Ethernet MAC –DES/AES Encryption –FIR/IIR Filters –Floating Point Unit

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QUALITY INTELLECTUAL PROPERTY

  • The VSI (Virtual Socket Interface) Alliance (VSIA) is

an open, international organization that includes representatives from all segments of the SoC industry: System houses, Semiconductor vendors, Electronic Design Automation (EDA) companies, and Intellectual Property (IP) providers. VSIA's mission is to dramatically enhance the productivity of the SoC design community.

  • Quality Intellectual Property (QIP) Metric v3.0 is

available for free from the VSIA website: www.vsia.org

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QIP METRICS

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DEVELOPING QUALITY IP

  • Requirements should be mapped into an executable specification

which produces the desired golden reference responses.

  • HDL and FPGA responses must match the golden responses

identically. HDL SOURCE CODE STIMULI FPGA MATLAB or C (fixed point) RESPONSES (golden ref.) RESPONSES (simulation) RESPONSES (system)

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  • Functional stimuli are developed by the designer to

mimic the system environment.

  • The tester is written in HDL but is not synthesized

into the FPGA.

THE TESTBENCH CONTAINS THE STIMULI, RESPONSES AND UUT

Testbench (Tester + HDL Source Code) Testbench (Tester + HDL Source Code)

HDL SOURCE CODE STIMULI (manual) RESPONSES Tester Tester

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  • Minimizing time-to-market encourages designers to develop only a

few tests for simulation and then proceed to testing the design inside the FPGA in its real-world environment. The FPGA executes tests 500x faster than the simulator and the real-world system environment produces the tests automatically.

RAPID VERIFICATION SAVES TIME

FPGA STIMULI (auto) RESPONSES (actual) HDL SOURCE CODE STIMULI (manual) RESPONSES Tester Tester SIMULATION REAL-WORLD SYSTEM ENVIRONMENT

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  • When errors are encountered on the FPGA board where

tests are limited to the primary inputs and primary outputs, the designer can return to simulation where complete controllability and observability of all of the internal nodes are available for debugging.

CONTROLLABILITY AND OBSERVABILITY AID DEBUGGING

Logic Gate Logic Gate Logic Gate

Primary Inputs Primary Output Internal Nodes Primary Inputs Primary Outputs

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POLISHING FOR REUSE

  • Once the HDL source code has been verified in the FPGA, the

design can be polished for reuse.

  • This involves documenting the HDL and providing test access

mechanisms for reuse as an embedded core per IEEE 1500: http://grouper.ieee.org/groups/1500

  • Also, the tester code should be enhanced with assertion-based

tests to achieve the desired HDL code coverage.

  • Constrained, random-generated tests can be produced

automatically for large HDL cores.

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The simulator can produce coverage reports and identify missed statements in the code.

COVERAGE-DRIVEN TESTS

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“Failure” stops simulation while “warning” does not. “Note” is used to document a correct response.

ASSERTION-BASED VERIFICATION

wait_clock(16); IF (left_seg = X"6")

  • - check second state of 7-segment display

THEN ASSERT false REPORT "Output signals set correctly (7-segment second state)" SEVERITY note; ELSE ASSERT false REPORT "Output not set correctly (7-segment second state)" SEVERITY warning; END IF; wait_clock(16); IF (left_seg = X"6")

  • - check second state of 7-segment display

THEN ASSERT false REPORT "Output signals set correctly (7-segment second state)" SEVERITY note; ELSE ASSERT false REPORT "Output not set correctly (7-segment second state)" SEVERITY warning; END IF;

The tester code should include stimuli and responses. The tester code should include stimuli and responses.

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BUILT-IN SELF-TEST CODE

  • The HDL source code can be augmented with Built-In Self-Test

(BIST) code.

  • BIST code can verify that the I/O and other likely failure

modes are working properly or not.

  • BIST code can also include functional test cases to assure

proper operation before execution or during “idle” times.

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GRAPHICAL TOOLS CAN REUSE AND CREATE IP BLOCKS

  • Library cells (basic IP blocks) are integrated

into a larger block that itself can be reused.

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  • STAR IP:

Blocks requiring 100+ staff years to design (like ARM, MIPS ) have become bestsellers and come with lots of support.

  • Small IP:

Blocks requiring 1-2 staff years to design are priced at 1/3 of the development cost. Buyers are skeptical about the value and often prefer to do these in-house.

  • Medium IP:

Blocks requiring 5-10 staff years are profitable for both seller and buyer. However, some suppliers have been bought by foundries to add to the foundries’ captive portfolios.

ACQUIRING IP

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ONCE UPON A TIME

Church County Road Dept. Pastor Snowy Road

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THE GLOBAL ECONOMY

The Earth is ……. Flat Boston or Bangalore or Knoxville Actually, we live on a small planet.

NOT

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COLLABORATIVE DESIGN

Collaborative Design of a System-on-Chip

http://www.cs.wright.edu/~tkprasad/courses/soc.html

Designer#2 Designer#1 Designer#3 Designer#4

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DESIGN-FOR-REUSE and DESIGN-WITH-REUSE

APPLICATION REQUIREMENTS

FPGA FPGA FPGA FPGA VERIFICATION DESIGN FOR REUSE HDL HDL HDL HDL TEAM PROJECT

SoC DESIGN WITH REUSE SYSTEM INTEGRATION

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SUMMARY AND CONCLUSIONS

  • Design Productivity
  • Intellectual Property Blocks
  • Reuse Requirements
  • The Changing Design Environment
  • Acquiring IP Blocks
  • Quality IP Metrics
  • Collaborative Design