SLIDE 1
Overview
¨ Notes
¤ Homework 8 is due Thursday (Mar. 28th)
n Verify your submitted file before midnight ¨ This lecture
¤ Single Cycle Processor ¤ Multi-Cycle/Pipelined Processor
CPU ORGANIZATION Mahdi Nazm Bojnordi Assistant Professor School of - - PowerPoint PPT Presentation
CPU ORGANIZATION Mahdi Nazm Bojnordi Assistant Professor School of - - PowerPoint PPT Presentation
CPU ORGANIZATION Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 3810: Computer Organization Overview Notes Homework 8 is due Thursday (Mar. 28 th ) n Verify your submitted file before midnight
SLIDE 2
SLIDE 3
Recall: Clocking the Processor
¨ Fetch unit is involved in processing all instructions
¤ Program counter (PC) and instruction memory
¨ Which of the units need a clock? ¨ What is being saved (latched) on the rising edge of the clock? ¨ The latched value remains there for an entire cycle
SLIDE 4
R-type Instructions
¨ Instructions of the form
¤ Example: add $t1, $t2, $t3
¨ Registers and ALU
SLIDE 5
I-type Instructions
¨ Instructions of the form
¤ Examples: lw $t1, 8($t2) and sw $t1, 8($t2)
¨ Registers, ALU, and data memory
¤ Where is the constant operand
SLIDE 6
I-type Instructions
¨ Instructions of the form
¤ Examples: lw $t1, 8($t2) and sw $t1, 8($t2)
¨ Registers, ALU, and data memory
¤ Where is the constant operand
SLIDE 7
J-type Instructions
¨ Instructions of the form
¤ Example: beq $t1, $t2, offset
SLIDE 8
The Processor Datapath
¨ Control signals are generated per instruction
SLIDE 9
The Single Cycle MIPS Processor
¨ A new PC is locked at the beginning of each cycle
SLIDE 10
Processing Instructions
¨ A sequence of processing tasks per instruction
SLIDE 11
Processing Instructions
¨ Every RISC instruction may
require multiple processing steps
¤ Instruction Fetch (IF) ¤ Instruction Decode (ID) ¤ Register Read (RR)
n All instructions?
¤ Execute Instructions (EXE) ¤ Memory Access (MEM)
n All instructions?
¤ Register Write Back (WB) Processor Memory instructions data functional units register file
SLIDE 12
Single-cycle MIPS Architecture
¨ Example: simple MIPS architecture
¤ Critical path includes all of the processing steps Write Back
- Inst. Fetch
- Inst. Decode
Execute Memory Inst. Memory Register File ALU Data Memory PC Controller
SLIDE 13
Single-cycle RISC Architecture
¨ Example program
¤ CT=6ns; CPU Time = ? AND $1,$2,$3 XOR $4,$2,$3 SUB $5,$1,$4 ADD $6,$1,$4 MUL $7,$5,$6 Time
SLIDE 14
Single-cycle RISC Architecture
¨ Example program
¤ CT=6ns; CPU Time = 5 x 6ns = 30ns Time
How to improve?
AND $1,$2,$3 XOR $4,$2,$3 SUB $5,$1,$4 ADD $6,$1,$4 MUL $7,$5,$6
SLIDE 15
Reusing Idle Resources
¨ Each processing step finishes in a fraction of a cycle
¤ Idle resources can be reused for processing next
instructions
Write Back
- Inst. Fetch
- Inst. Decode
Execute Memory Inst. Memory Register File ALU Data Memory PC
SLIDE 16
Pipelined Architecture
¨ Five stage pipeline
¤ Critical path determines the cycle time Write Back
- Inst. Fetch
- Inst. Decode
Execute Memory Inst. Memory Register File ALU Data Memory PC 1.5ns 1.5ns 1.25ns 1.05ns 0.7ns