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Some of Our Related Work
1.
- X. Zheng, F.C.M. Lau and C.K. Tse, “Error Performance of Short-Block-Length
LDPC Code Built on Scale-Free Networks,” Proceedings, The Third Shanghai International Symposium on Nonlinear Sciences and Applications, Shanghai, China, June 2007, pp. 55-57. 2.
- X. Zheng, F.C.M. Lau, Chi K. Tse and S.C. Wong, “Study of Bifurcation
Behavior of LDPC Decoders", International Journal of Bifurcation and Chaos,
- vol. 16, no. 11, pp. 3435-3449, Nov. 2006.
3.
- X. Zheng, F.C.M. Lau and Chi K. Tse, “Study of LDPC Codes Built on Scale-
Free Networks,” Proceedings, International Symposium on Nonlinear Theory and Its Applications (NOLTA'06), Bologna, Italy, September 2006, pp. 563-566. 4.
- X. Zheng, F.C.M. Lau, C.K. Tse and S.C. Wong, “Techniques for Improving
Block Error Rate of LDPC Decoders,” Proceedings, IEEE International Symposium on Circuits and Systems (ISCAS'06), Kos, Greece, May 2006, pp. 2261-2264. 5.
- X. Zheng, F.C.M. Lau, Chi K. Tse and S.C. Wong, “Study of Nonlinear
Dynamics of LDPC Decoders", Proceedings, European Conference on Circuit Theory and Design (ECCTD ‘2005), Dublin, Ireland, August 2005, paper 207. (CD version)