Computer System Architecture User program plus Data Main ADD - PowerPoint PPT Presentation

“Macroinstruction” Interpretation Computer System Architecture User program plus Data Main ADD Memory SUB this can change! AND Processor Part IV . . . one of these is DATA mapped into one of these execution unit Chalermek Intanagonwiwat AND microsequence CPU control memory e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Slides courtesy of John Hennessy and David Patterson Save Answer(s) Microprogramming Microprogramming Pros and Cons Control unit PCWrite PCWriteCond IorD • Ease of design MemRead Microcode memory Datapath MemWrite IRWrite • Flexibility BWrite Outputs MemtoReg PCSource ALUOp – Easy to adapt to changes in organization, ALUSrcB ALUSrcA timing, technology RegWrite RegDst AddrCtl – Can make changes late in design cycle, or Input 1 even in the field Microprogram counter • Can implement very powerful instruction Adder Address select logic sets (just more control memory) ] 0 – 5 [ p O Instruction register opcode field 1

Microprogramming Pros and Cons Exceptions (cont.) • Generality System user program Exception – Can implement multiple instruction sets on Handler Exception: same machine. – Can tailor instruction set to application. • Compatibility – Many organizations, same instruction set return from exception • Slow normal control flow: sequential, jumps, branches, calls, returns Two Types of Exceptions Exceptions (cont.) • Exception = unprogrammed control • Interrupts transfer – caused by external events – system takes action to handle the – asynchronous to program execution exception – may be handled between instructions • must record the address of the offending – simply suspend and resume user program instruction – returns control to user – must save & restore user state 2

Two Types of Exceptions MIPS Convention (cont.) Type of event From where? MIPS terminology I/O device request External Interrupt • Traps – caused by internal events Invoke OS from user • exceptional conditions (overflow) program Internal Exception • errors (parity) • faults (non-resident page) Arithmetic overflow Internal Exception – synchronous to program execution Using an undefined – condition must be remedied by the handler instruction Internal Exception – instruction may be retried or simulated and program continued or program may be aborted Addressing the Exception Addressing the Exception Handler Handler (cont.) • RISC Handler Table • Traditional Approach: Interupt Vector – PC <– IV_base + cause || 0000 – PC <- MEM[ IV_base + cause || 00] – saves state and jumps – E.g., Vax, 80x86 – E.g., Sparc handler handler entry code code iv_base cause iv_base cause 3

Addressing the Exception Saving State Handler (cont.) • Push it onto the stack – Vax, 68k, 80x86 • Save it in special registers • MIPS Approach: fixed entry – MIPS EPC, BadVaddr, Status, Cause – PC <– EXC_addr • Shadow Registers – M88k – Save state in a shadow of the internal pipeline registers Additions to MIPS ISA to Additions to MIPS ISA to support Exceptions? support Exceptions? (cont.) • EPC–a 32-bit register used to hold the address • BadVAddr - register contained memory of the affected instruction address at which memory reference occurred • Cause–a register used to record the cause of • Status - interrupt mask and enable bits the exception. – In the MIPS architecture this register is 32 bits, • Control signals to write EPC , Cause, though some bits are currently unused. BadVAddr, and Status – Assume that bits 5 to 2 of this register encodes the two possible exception sources mentioned above: • undefined instruction=0 and arithmetic overflow=1 4

Additions to MIPS ISA to Precise Interrupts support Exceptions? (cont.) • Precise => state of the machine is preserved as if program executed upto • Be able to write exception address into PC, increase mux to add as input 01000000 the offending instruction 00000000 00000000 01000000 two (8000 – Same system code will work on different 0080 hex ) implementations of the architecture – Difficult in the presence of pipelining, out-ot- • May have to undo PC = PC + 4, since want EPC order execution, ... to point to offending instruction (not its – MIPS takes this position successor); PC = PC - 4 How Control Detects Precise Interrupts (cont.) Exceptions in our FSM • Imprecise => system software has to • Undefined Instruction–detected when no figure out what is where and put it all next state is defined from state 1 for the back together op value. • Performance goals often lead designers to – We handle this exception by defining the forsake precise interrupts next state value for all op values other than lw, sw, 0 (R-type), jmp, beq, and ori as new – system software developers, user, markets state 12. etc. usually wish they had not done this – Shown symbolically using “other” to indicate that the op field does not match any of the opcodes that label arcs out of state 1. 5

How Control Detects Modification to the Control Specification Exceptions in our FSM (cont.) IR <= MEM[PC] undefined instruction PC <= PC + 4 • Arithmetic overflow EPC <= PC - 4 A <= R[rs] PC <= exp_addr other – Chapter 4 (HW/SW book) included logic in B <= R[rt] cause <= 10 (RI) the ALU to detect overflow, and a signal BEQ LW R-type ORi SW called Overflow is provided as an output from S <= A - B ~Equal the ALU. S <= A fun B S <= A op ZX S <= A + SX S <= A + SX 0010 Equal – This signal is used in the modified finite state overflow PC <= PC + M <= MEM[S] MEM[S] <= B machine to specify an additional possible next SX || 00 0011 state R[rd] <= S R[rt] <= S R[rt] <= M Additional condition from EPC <= PC - 4 Datapath PC <= exp_addr cause <= 12 (Ovf) Summary Summary (cont.) • Need to find convenient place to detect • Specialize state-diagrams easily captured exceptions and to branch to state or by microsequencer microinstruction that saves PC and – simple increment & “branch” fields invokes the operating system – datapath control fields • As we get pipelined CPUs that support • Control design reduces to page faults on memory accesses which Microprogramming means that the instruction cannot complete AND you must be able to • Exceptions are the hard part of control restart the program at exactly the instruction with the exception, it gets even harder 6

Summary: Microprogramming Summary: Microprogramming one inspiration for RISC one inspiration for RISC (cont.) • If simple instruction could execute at very • If same memory used for control memory high clock rate… could be used instead as cache for • If you could even write compilers to “macroinstructions”… produce microinstructions… • Then why not skip instruction • If most programs use simple instructions interpretation by a microprogram and and addressing modes… simply compile directly into lowest language of machine? • If microcode is kept in RAM instead of ROM so as to fix bugs … 7