Computer Architecture Appendix B Fall 2005 Department of Computer - - PowerPoint PPT Presentation

Computer Architecture

Appendix B

Fall 2005 Department of Computer Science Kent State University

Logic Values

• Logic '0'

– False, off, deasserted, low

• Logic '1'

– True, on, asserted, high

Combinational vs. Sequential

• Logic is combinational if its outputs are

determined entirely by its current inputs

• Logic is sequential if its outputs are

determined by its current inputs and any past inputs

• Sequential logic has memory or state which

allows it to remember past inputs

Combinational Logic

• Built from gates
• Can be described using a truth table or a

Boolean equation

• It is possible to translate between all three

representations

AND Gate

1 1 1 1 1 F B A

F=A⋅B

OR Gate

1 1 1 1 1 1 1 F B A

F=AB

NOT Gate

1 1 F A

F= A

Inversion Bubbles

• Inverters are so commonly used that designers

have developed a shorthand notation

• Instead of using explicit inverters, you can attach

bubbles to the inputs or outputs of other gates

B A A B

Combinational logic

• How would your describe the output of this

combinational logic circuit?

NAND Gate

• The NAND gate is the combination of an

NOT gate with an AND gate.

The Bubble in front of the gate is an inverter.

Combinational logic

• How would your describe the output of this

combinational logic circuit?

NOR gate

• The NOR gate is the combination of the

NOT gate with the OR gate.

The Bubble in front of the gate is an inverter.

NAND and NOR gates

• The NAND and NOR gates are very

popular as they can be connected in more ways that the simple AND and OR gates.

Exercise 1 – a bit challenging

Complete the Truth Table for the NAND and NOR Gates

1 1 1 1 Output Input 1 1 1 1 Output Input NAND NOR

Hint: Think of the AND and OR truth tables. The outputs for the NAND and NOR are inverted.

Exercise 2 – more challenging

• Turn the NAND and NOR gates into

inverter (NOT) gates. Include a switch for the input.

Universal Gates

• Any combinational function can be built

from AND, OR and NOT gates

• However, there are universal gates that

alone can implement any function

• NAND and NOR are two such gates
• NAND and NOR are AND and OR gates

with inverted outputs

Combining Logic Gates

Add the boolean expressions at the output for each AND gate

A B Y C A•B B•C

Combining Logic Gates Next add the boolean expressions at the output for the OR gate

The Boolean expression for the complete logic circuit is: Y = (A•B)+(B•C)

B•C A B Y C A•B (A•B) + (B•C)

Combining Logic: Truth Table Given : Y = (A•B)+(B•C)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y C B A

Laws of Boolean Algebra , Babbage(B.3,pB6)

· Identity law: A + 0 = A and A • 1 = A · Zero and One laws: A + 1 = 1 and A • 0 = 0 · Inverse Laws: A + A = 1 and A • A = 0 · Commutative laws: A + B = B + A and A • B = B • A (switch inputs) · Associative laws: A + (B + C) = (A + B) + C and A • (B • C) = (A • B) • C (reorder inputs) · Distributive laws: A • (B + C) = (A • B) + (A • C) and A + (B • C) = (A + B) • (A + C) _____ __ __ · De Morgan’s laws: (A + B) = (A) • (B) and _____ __ __ (A • B) = (A) + (B) (invert inputs)

Decoder

• A decoder asserts exactly
• ne of its 2n outputs for

each combination of its n inputs

• The n inputs are

interpreted as an n-bit binary number

• A decoder with n inputs

and 2n outputs is called a n-to-2n decoder (eg, a 3-to- 8 decoder)

Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 Decoder

• a. A 3-bit decoder

3

Decoder Truth Table

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

• 1
• 2
• 3
• 4
• 5
• 6
• 7

i0 i1 i2 Outputs Inputs

Multiplexer

1 A C B S M u x C A B S

• A multiplexer selects one of its 2n data inputs, based on the

value of its n selector inputs, to become its output

• The n selector inputs are interpreted as an n-bit binary

number

• A multiplexer with n inputs is called an n-to-1 multiplexer

(eg, a 4-to-1 multiplexer)

Arrays of Logic Elements

M u x Select 32 A 32 B 32 C M u x Select A31 B31 C31 M u x A30 B30 C30 M u x A0 B0 C0

• b. The 32-bit wide multiplex is actually

an array of 32 1-bit multiplexors

• a. A 32-bit wide 2-to-1 multiplexor

Review-1

• Universal Gate
• Decoder
• Multiplexor

= = = =

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• Problem: Consider a logic function with three inputs: A, B, and C.

Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true

• Show the truth table for these three functions.
• Show the Boolean equations for these three functions.
• Show an implementation consisting of inverters, AND, and OR gates.

Review-2

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Lets Build a Processor

• ALU

32 32 32

• peration

result a b

ALU

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• Let's build an ALU to support the andi and ori instructions

– we'll just build a 1 bit ALU, and use 32 of them

• Possible Implementation (sum-of-products):

b a

• peration

result

• p a

b res

An ALU (arithmetic logic unit)

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• Selects one of the inputs to be the output, based on a control input
• Lets build our ALU using a MUX:

S C A B

1

Review: The Multiplexor

note: we call this a 2-input mux even though it has 3 inputs!

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• Not easy to decide the “best” way to build something

– Don't want too many inputs to a single gate – Don’t want to have to go through too many gates – for our purposes, ease of comprehension is important

• Let's look at a 1-bit ALU for addition:
• How could we build a 1-bit ALU for add, and, and or?
• How could we build a 32-bit ALU?

Different Implementations

cout = a b + a cin + b cin sum = a xor b xor cin

Sum CarryIn CarryOut a b

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Decoder Truth Table

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

• 1
• 2
• 3
• 4
• 5
• 6
• 7

i0 i1 i2 Outputs Inputs

Review Question: how to build a decoder?

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Building a 32 bit ALU

b 2 Result Operation a 1 CarryIn CarryOut

Result31 a31 b31 Result0 CarryIn a0 b0 Result1 a1 b1 Result2 a2 b2 Operation ALU0 CarryIn CarryOut ALU1 CarryIn CarryOut ALU2 CarryIn CarryOut ALU31 CarryIn

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• Two's complement approach: just negate b and add.
• How do we negate?
• A very clever solution:

What about subtraction (a – b) ?

2 Result Operation a 1 CarryIn CarryOut 1 Binvert b

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Adding a NOR function

• Can also choose to invert a. How do we get “a NOR b” ?

Binvert a b CarryIn CarryOut Operation 1 2 + Result 1 Ainvert 1

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• Need to support the set-on-less-than instruction (slt)

– remember: slt is an arithmetic instruction – produces a 1 if rs < rt and 0 otherwise – use subtraction: (a-b) < 0 implies a < b

• Need to support test for equality (beq $t5, $t6, $t7)

– use subtraction: (a-b) = 0 implies a = b

Tailoring the ALU to the MIPS

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Supporting slt

• Can we figure out the idea?

Binvert a b CarryIn CarryOut Operation 1 2 + Result 1 Ainvert 1 3 Less Binvert a b CarryIn Operation 1 2 + Result 1 3 Less Overflow detection Set Overflow Ainvert 1

Use this ALU for most significant bit all other bits

a0 Operation CarryIn ALU0 Less CarryOut b0 CarryIn a1 CarryIn ALU1 Less CarryOut b1 Result0 Result1 a2 CarryIn ALU2 Less CarryOut b2 a31 CarryIn ALU31 Less b31 Result2 Result31 . . . . . . . . . Binvert Ainvert Overflow Set CarryIn

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Test for equality

• Notice control lines:

0000 = and 0001 = or 0010 = add 0110 = subtract 0111 = slt 1100 = NOR

• Note: zero is a 1 when the result is zero!

a0 Operation CarryIn ALU0 Less CarryOut b0 a1 CarryIn ALU1 Less CarryOut b1 Result0 Result1 a2 CarryIn ALU2 Less CarryOut b2 a31 CarryIn ALU31 Less b31 Result2 Result31 . . . . . . . . . Bnegate Ainvert Overflow Set CarryIn . . . . . . Zero

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Conclusion

• We can build an ALU to support the MIPS instruction set

– key idea: use multiplexor to select the output we want – we can efficiently perform subtraction using two’s complement – we can replicate a 1-bit ALU to produce a 32-bit ALU

• Important points about hardware

– all of the gates are always working – the speed of a gate is affected by the number of inputs to the gate – the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”)

• Our primary focus: comprehension, however,

– Clever changes to organization can improve performance (similar to using better algorithms in software) – We saw this in multiplication, let’s look at addition now

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ALU Summary

• We can build an ALU to support MIPS addition
• Our focus is on comprehension, not performance
• Real processors use more sophisticated techniques for arithmetic
• Where performance is not critical, hardware description languages

allow designers to completely automate the creation of hardware!

Bonus Question – 2 point

• Write a C/C++ program which accepts an

unsigned integer, a signed integer, or a floating point, and output the 32 bits binary number.

• Run this program with several examples we

discussed in the class and see if the results are indeed as we discussed.

Sequential Logic

• Sequential logic is built from flip-flops and

latches in addition to combinational gates

• What’s are and flip-flops? – State Element
• Most of the sequential logic rely on clocks

Clocks

• A clock is a logic signal that oscillates

between 0 and 1 with a fixed frequency

• When the clock transitions from 0 to 1, this

is called a rising edge; a transition from 1 to 0 is a falling edge

• Logic can be built to respond to the value of

the clock (level-sensitive) or to its edges (edge-sensitive)

Clocks

Clock period Rising edge Falling edge

• The clock frequency is the inverse of the clock

period (or cycle time)

• Example: a 100 MHz clock has a period of 10 ns

• The set-reset latch

– output depends on present inputs and also on past inputs

An unclocked state element

R S Q Q

• Two inputs:

– the data value to be stored (D) – the clock signal (C) indicating when to read & store D

• Two outputs:

– the value of the internal state (Q) and it's complement

D-latch

Latch Example

D C Q

Q C D _ Q

Latches

• Latches are level-sensitive storage elements
• A latch stores a single bit
• The value stored in a latch is updated

continuously while the clock is high

– We say that the latch is transparent

• The latch's stored value remains the same

while the clock is low

Flip-Flop

• Flip-flops are edge-sensitive storage elements
• A flip-flop stores a single bit
• The value stored in a flip-flop is updated at the

rising (or falling) edge of the clock

• Any other time the value stored in the flip-flop

will remain unchanged

• A flip-flop may also have an enable input; the flip-

flop then updates its stored value only on a clock edge when the enable signal is high

Flip-Flop Example

D C Q

Registers

• We can build an n-bit register from an array
• f n flip-flops
• Each flip-flop holds one bit of the value
• All flip-flops use the same clock and enable

inputs

Register Files

• An array of registers
• Multiple ports allow

multiple simultaneous reads and writes

• Used to implement

general-purpose registers in MIPS

Read register number 1 Read data 1 Read data 2 Read register number 2

Register file

Write register Write data Write

Register File Read Ports

M u x Register 0 Register 1 Register n – 1 Register n M u x Read data 1 Read data 2 Read register number 1 Read register number 2

Register File Write Port

n-to-1 decoder Register 0 Register 1 Register n – 1 C C D D Register n C C D D Register number Write Register data 1 n – 1 n

Mixed Logic

• Typically we see

combinational logic placed between registers

• Using edge-triggered

elements, the outputs can be sent back to the same register

Clock cycle State element 1 Combinational logic State element 2

State element Combinational logic

Timing Issues

• In sequential logic, inputs must be stable before the clock

edge (setup time) and after (hold time)

• It also takes time for the clock signal to propagate (skew)
• These constrain the clock period

D C Set-up time Hold time

Multiplication



Recall:

1000ten X 1001ten 1000

0000

0000 1000 1001000ten

Observations



More storage required to store the product



Place copy of multiplicand in proper location if multiplier is a 1



Place 0 in proper location if multiplier is 0



Product of n-bit Multiplicand and m-Multiplier is (n + m)-bit long



Number of steps (move digits to LHS) is n -1; where n rep the number of digits (1,0)

Let's examine 2 versions of multiplication algorithm for binary numbers

Multiplicand Multiplier Product

Multiplication

Version 1

Multiplicand Shift left 64 bits 64-bit ALU Product Write 64 bits Control test Multiplier Shift right 32 bits

32nd repetition?

• 1a. Add multiplicand to product and

place the result in Product register Multiplier0 = 0

• 1. Test

Multiplier0 Start Multiplier0 = 1

• 2. Shift the Multiplicand register left 1 bit
• 3. Shift the Multiplier register right 1 bit

No: < 32 repetitions Yes: 32 repetitions Done

Datapath Control

Multiplication

Refined Version

Multiplicand 32 bits 32-bit ALU Product Write 64 bits Control test Shift right

32nd repetition? Product0 = 0

• 1. Test

Product0 Start Product0 = 1

• 3. Shift the Product register right 1 bit

No: < 32 repetitions Yes: 32 repetitions Done

Add multiplicand to product and place the result in ?