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Chapter 3 Professor Brendan Morris, SEB 3216, - - PowerPoint PPT Presentation

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Chapter 3 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/ CPE100: Digital Logic Design I Section 1004: Dr. Morris Sequential Logic Design Chapter 3 <1> Chapter 3 :: Topics

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SLIDE 1

Chapter 3 <1>

Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/

Chapter 3

CPE100: Digital Logic Design I

Section 1004: Dr. Morris Sequential Logic Design

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SLIDE 2

Chapter 3 <2>

Chapter 3 :: Topics

  • Introduction
  • Latches and Flip-Flops
  • Synchronous Logic Design
  • Finite State Machines
  • Timing of Sequential Logic
  • Parallelism
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SLIDE 3

Chapter 3 <3>

  • Previously, Combinational Logic design had
  • utputs only depend on current value of inputs
  • Outputs of sequential logic depend on current

and prior input values – it has memory.

  • Some definitions:
  • State: all the information about a circuit necessary to

explain its future behavior

  • Latches and flip-flops: state elements that store one

bit of state

  • Synchronous sequential circuits: combinational logic

followed by a bank of flip-flops

Introduction

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SLIDE 4

Chapter 3 <4>

  • Give sequence to events (i.e. a notion of time)
  • Have memory (short-term)
  • Use feedback from output to input to store

information

  • Need to “remember” past output

Sequential Circuits

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SLIDE 5

Chapter 3 <5>

  • The state of a circuit influences its future

behavior

  • State elements store state
  • Bistable circuit
  • SR Latch
  • D Latch
  • D Flip-flop

State Elements

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SLIDE 6

Chapter 3 <6>

Q Q Q Q I1 I2 I2 I1

  • Fundamental building block of other state

elements

  • Two outputs: Q, Q (state)
  • No inputs

Bistable Circuit

0 1 0 1 0 1 Redrawn circuit to emphasize symmetry

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SLIDE 7

Chapter 3 <7>

Q Q I1 I2 1 1

  • Consider the two possible cases:
  • Q = 0:

then Q = 1, Q = 0 (consistent)

Bistable Circuit Analysis

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SLIDE 8

Chapter 3 <8>

Q Q I1 I2 1 1 Q Q I1 I2 1 1

  • Consider the two possible cases:
  • Q = 0:

then Q = 1, Q = 0 (consistent)

  • Q = 1:

then Q = 0, Q = 1 (consistent)

  • Stores 1 bit of state in the state variable, Q (or Q)
  • But there are no inputs to control the state

Bistable Circuit Analysis

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SLIDE 9

Chapter 3 <9>

R S Q Q N1 N2

  • SR Latch
  • S – set Q=1
  • R – reset Q=0

SR (Set/Reset) Latch

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SLIDE 10

Chapter 3 <10>

R S Q Q N1 N2

  • SR Latch
  • Consider the four possible cases:
  • S = 1, R = 0
  • S = 0, R = 1
  • S = 0, R = 0
  • S = 1, R = 1

SR (Set/Reset) Latch

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SLIDE 11

Chapter 3 <11>

  • S = 1, R = 0:

then Q = 1 and Q = 0

SR Latch Analysis

R S Q Q N1 N2 1 1

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SLIDE 12

Chapter 3 <12>

  • S = 1, R = 0:

then Q = 1 and Q = 0

SR Latch Analysis

R S Q Q N1 N2 1 1

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SLIDE 13

Chapter 3 <13>

  • S = 1, R = 0:

then Q = 1 and Q = 0

  • S = 0, R = 1:

then Q = 0 and Q = 1

SR Latch Analysis

R S Q Q N1 N2 1 1 R S Q Q N1 N2 1 1 1

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SLIDE 14

Chapter 3 <14>

  • S = 1, R = 0:

then Q = 1 and Q = 0 Set the output

  • S = 0, R = 1:

then Q = 0 and Q = 1 Reset the output

SR Latch Analysis

R S Q Q N1 N2 1 1 R S Q Q N1 N2 1 1 1

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SLIDE 15

Chapter 3 <15>

R S Q Q N1 N2 R S Q Q N1 N2 Qprev = 0 Qprev = 1 1

  • S = 0, R = 0:

then Q = Qprev

SR Latch Analysis

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SLIDE 16

Chapter 3 <16>

R S Q Q N1 N2 R S Q Q N1 N2 Qprev = 0 Qprev = 1 1

  • S = 0, R = 0:

then Q = Qprev

SR Latch Analysis

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SLIDE 17

Chapter 3 <17>

R S Q Q N1 N2 R S Q Q N1 N2 Qprev = 0 Qprev = 1 1

  • S = 0, R = 0:

then Q = Qprev

  • S = 1, R = 1:

then Q = 0, Q = 0

SR Latch Analysis

R S Q Q N1 N2 1 1

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SLIDE 18

Chapter 3 <18>

R S Q Q N1 N2 R S Q Q N1 N2 Qprev = 0 Qprev = 1 1

  • S = 0, R = 0:

then Q = Qprev

  • S = 1, R = 1:

then Q = 0, Q = 0

SR Latch Analysis

R S Q Q N1 N2 1 1

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SLIDE 19

Chapter 3 <19>

R S Q Q N1 N2 R S Q Q N1 N2 Qprev = 0 Qprev = 1

  • S = 0, R = 0:

then Q = Qprev Memory!

  • S = 1, R = 1:

then Q = 0, Q = 0 Invalid State Q ≠ NOT Q

SR Latch Analysis

R S Q Q N1 N2 1 1

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SLIDE 20

Chapter 3 <20>

S R Q Q SR Latch Symbol

  • SR stands for Set/Reset Latch

– Stores one bit of state (Q)

  • Control what value is being stored with S, R

inputs

  • Set: Make the output 1

(S = 1, R = 0, Q = 1)

  • Reset: Make the output 0

(S = 0, R = 1, Q = 0)

  • SR Latch Symbol
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SLIDE 21

Chapter 3 <21>

D Latch Symbol CLK D Q Q

  • Two inputs: CLK, D
  • CLK: controls when the output changes
  • D (the data input): controls what the output changes to
  • Function
  • When CLK = 1,

D passes through to Q (transparent)

  • When CLK = 0,

Q holds its previous value (opaque)

  • Avoids invalid case when

Q ≠ NOT Q

D Latch

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SLIDE 22

Chapter 3 <22>

S R Q Q Q Q D CLK

D R S

CLK D Q Q

S R Q Q CLK D X 1 1 1 D

D Latch Internal Circuit

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SLIDE 23

Chapter 3 <23>

S R Q Q Q Q D CLK

D R S

CLK D Q Q

S R Q Qprev 1 1 1 Q 1 CLK D X 1 1 1 D X 1 Qprev

D Latch Internal Circuit

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SLIDE 24

Chapter 3 <24>

D Flip-Flop Symbols D Q Q

  • Inputs: CLK, D
  • Function

– Samples D on rising edge of CLK

  • When CLK rises from 0 to 1, D

passes through to Q

  • Otherwise, Q holds its previous

value – Q changes only on rising edge of CLK

  • Called edge-triggered
  • Activated on the clock edge

D Flip-Flop

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SLIDE 25

Chapter 3 <25>

CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

  • Two back-to-back latches (L1 and L2) controlled by

complementary clocks

  • When CLK = 0
  • L1 is transparent
  • L2 is opaque

– D passes through to N1

D Flip-Flop Internal Circuit

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SLIDE 26

Chapter 3 <26>

CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

  • Two back-to-back latches (L1 and L2) controlled by

complementary clocks

  • When CLK = 0

– L1 is transparent – L2 is opaque – D passes through to N1

  • When CLK = 1

– L2 is transparent – L1 is opaque – N1 passes through to Q

D Flip-Flop Internal Circuit

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SLIDE 27

Chapter 3 <27>

CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

  • Two back-to-back latches (L1 and L2) controlled by

complementary clocks

  • When CLK = 0

– L1 is transparent – L2 is opaque – D passes through to N1

  • When CLK = 1

– L2 is transparent – L1 is opaque – N1 passes through to Q

  • Thus, on the edge of the clock (when CLK rises from 0 1)

– D passes through to Q

D Flip-Flop Internal Circuit

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SLIDE 28

Chapter 3 <28>

CLK D Q Q D Q Q

CLK D Q (latch) Q (flop)

D Latch vs. D Flip-Flop

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SLIDE 29

Chapter 3 <29> CLK D Q (latch) Q (flop)

D Latch vs. D Flip-Flop

CLK D Q Q D Q Q

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SLIDE 30

Chapter 3 <30>

Review

S R Q Q SR Latch Symbol

CLK D Q Q

D Q Q

SR Latch D Latch D Flip-flop

S = 1, R = 0: Q = 1 S = 0, R= 1: Q = 0 CLK = 1: Q = D CLK = 0: Q = Qprev CLK = 0→1: Q = D Otherwise: Q = Qprev

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SLIDE 31

Chapter 3 <31>

CLK D Q D Q D Q D Q D0 D1 D2 D3 Q0 Q1 Q2 Q3

D3:0

4 4

CLK Q3:0

Registers

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SLIDE 32

Chapter 3 <32>

Internal Circuit D Q CLK EN D Q 1 D Q EN Symbol

  • Inputs: CLK, D, EN

– The enable input (EN) controls when new data (D) is stored

  • Function
  • EN = 1: D passes through to Q on the clock edge
  • EN = 0: the flip-flop retains its previous state

Enabled Flip-Flops

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SLIDE 33

Chapter 3 <33>

Internal Circuit D Q CLK EN D Q 1 D Q EN Symbol

  • Inputs: CLK, D, EN

– The enable input (EN) controls when new data (D) is stored

  • Function
  • EN = 1: D passes through to Q on the clock edge
  • EN = 0: the flip-flop retains its previous state

Enabled Flip-Flops

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SLIDE 34

Chapter 3 <34>

Symbols D Q

Reset r

  • Inputs: CLK, D, Reset
  • Function:
  • Reset = 1: Q is forced to 0
  • Reset = 0: flip-flop behaves as ordinary D flip-flop

Resettable Flip-Flops

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SLIDE 35

Chapter 3 <35>

  • Two types:

– Synchronous: resets at the clock edge only – Asynchronous: resets immediately when Reset = 1

  • Asynchronously resettable flip-flop requires

changing the internal circuitry of the flip-flop

  • Synchronously resettable flip-flop?

Resettable Flip-Flops

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SLIDE 36

Chapter 3 <36>

  • Two types:

– Synchronous: resets at the clock edge only – Asynchronous: resets immediately when Reset = 1

  • Asynchronously resettable flip-flop requires

changing the internal circuitry of the flip-flop

  • Synchronously resettable flip-flop?

Resettable Flip-Flops

Internal Circuit D Q CLK D Q Reset

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SLIDE 37

Chapter 3 <37>

Symbols D Q

Set s

  • Inputs: CLK, D, Set
  • Function:
  • Set = 1: Q is set to 1
  • Set = 0: the flip-flop behaves as ordinary D flip-

flop

Settable Flip-Flops

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SLIDE 38

Chapter 3 <38>

  • Registers inserted between combinational

logic

  • Registers contain state of the system
  • State changes at clock edge: system

synchronized to the clock

Synchronous Sequential Logic Design

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SLIDE 39

Chapter 3 <39>

  • Rules of synchronous sequential circuit

composition:

  • Every circuit element is either a register or a

combinational circuit

  • At least one circuit element is a register
  • All registers receive the same clock signal
  • Every cyclic path contains at least one register

Synchronous Sequential Logic Design

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SLIDE 40

Chapter 3 <40>

  • Rules of synchronous sequential circuit

composition:

  • Every circuit element is either a register or a

combinational circuit

  • At least one circuit element is a register
  • All registers receive the same clock signal
  • Every cyclic path contains at least one register
  • Two common synchronous sequential circuits
  • Finite State Machines (FSMs)
  • Pipelines

Synchronous Sequential Logic Design