[PPT] - Challenges & Strategies for the SPICE Model Extraction & PowerPoint Presentation

SLIDE 1

Compact Modeling & Characterization Group

Microprocessor Solutions Sector, Sunnyvale, CA

Advanc e d Mic r

De vic e s

Challenges & Strategies for the SPICE Model Extraction & Simulation of the PD-SOI Technology

Jung- Suk Goo

SLIDE 2

20/ 09/ 05 MOS-AK 2005 2

Outline

! Bulk CMOS vs. PD-SOI CMOS ! Self-heating ! Floating-Body Modeling: History-Effect

! Definition ! Underlying Physics ! Key Components & Their Impacts

! Parameter Extraction Flow ! Challenges in Measurement & Extraction ! Tied-Body Modeling

! History–Effect in Tied-Body CMOS ! Parasitic Gate Capacitance ! Distributed Body Resistance

! Conclusion

SLIDE 3

20/ 09/ 05 MOS-AK 2005 3

Outline

! Bulk CMOS vs. PD-SOI CMOS ! Self-heating ! Floating-Body Modeling: History-Effect

! Definition ! Underlying Physics ! Key Components & Their Impacts

! Parameter Extraction Flow ! Challenges in Measurement & Extraction ! Tied-Body Modeling

! History–Effect in Tied-Body CMOS ! Parasitic Gate Capacitance ! Distributed Body Resistance

! Conclusion

SLIDE 4

20/ 09/ 05 MOS-AK 2005 4

Bulk CMOS vs. PD-SOI CMOS

! The chief difference of the PD-SOI is that the body of each SOI transistor is an independent 4th terminal for the device ! When absolutely needed, the body can be fixed to a chosen potential with a body tie: ! However, in 99.9% of the chip, transistors will be operating as floating body devices Bulk CMOS Identical body potential PD- SOI CMOS

Floating Body Transistor Transistor with body tie Floating Body Transistor Transistor with body tie

Independent body potential

SLIDE 5

20/ 09/ 05 MOS-AK 2005 5

Self-Heating

! Thermal conductivity

! Ksi = 60 - 148W/mK ! Kox = 0.2 - 1.2W/mK

! Relatively poor modeling ! Occasional convergence issue

0.4 0.8 1.2 1.6 2

Drain Voltage(V)

3E-4 6E-4 9E-4 1.2E-3 1.5E-3

Drain Current (A/um)

without self-heating with self-heating

Vgs=0.5 V Vgs=1.0 V Vgs=1.5 V Vgs=2.0 V

0.4 0.8 1.2 1.6 2

Drain Voltage(V)

3E-4 6E-4 9E-4 1.2E-3 1.5E-3

Drain Current (A/um)

without self-heating with self-heating

Vgs=0.5 V Vgs=1.0 V Vgs=1.5 V Vgs=2.0 V

0.4 0.8 1.2 1.6 2

Drain Voltage(V)

3E-4 6E-4 9E-4 1.2E-3 1.5E-3

Drain Current (A/um)

without self-heating with self-heating

Vgs=0.5 V Vgs=1.0 V Vgs=1.5 V Vgs=2.0 V

Po we r Rth Cth

SLIDE 6

20/ 09/ 05 MOS-AK 2005 6

Outline

! Bulk CMOS vs. PD-SOI CMOS ! Self-heating ! Floating-Body Modeling: History-Effect

! Definition ! Underlying Physics ! Key Components & Their Impacts

! Parameter Extraction Flow ! Challenges in Measurement & Extraction ! Tied-Body Modeling

! History–Effect in Tied-Body CMOS ! Parasitic Gate Capacitance ! Distributed Body Resistance

! Conclusion

SLIDE 7

20/ 09/ 05 MOS-AK 2005 7

CMOS Inverter Operation

SLIDE 8

20/ 09/ 05 MOS-AK 2005 8

Definition of History-Effect

! 1st switch: input transition after being held constant for a long time. ! 2nd switch: input transition short time after the 1st switch.

τ 1st τ 2nd

History-effect H = (τ 1st – τ 2nd) / τ 2nd

SLIDE 9

20/ 09/ 05 MOS-AK 2005 9

Typical History-Effect

! Delay is subject to switching history

f the logic gate.

Input Cloc k Shape

Dynamic Ste ady State 2nd SW 1st SW

10

10

10

9

10

8

10

7

10

6

10

5

10

4

10 11 12 13 14 15 Time [s] Delay/Stage [ps]

tr=tf=0.8ns tper=40ns (50% duty) step=100ps

E volution of Switc hing De lay

SLIDE 10

20/ 09/ 05 MOS-AK 2005 10

What Causes History-Effect?

! Body Potential is a function of:

! Capacitive coupling to

! Source ! Drain ! Gate ! Substrate (small)

! Diode Leakages to

! Source ! Drain

! Gate Leakage ! Impact Ionization

! Also subject to the previous

switching history

Source Drain Substrate Buried Oxide

SLIDE 11

20/ 09/ 05 MOS-AK 2005 11

Combined Capacitive/Resistive Network

R1 C1 R2 C2 T ime Vo ltag e

R-Divider C-Divider RC Decay

SLIDE 12

20/ 09/ 05 MOS-AK 2005 12

Time for Actual Contribution to Speed

! 1st SW : Initial DC ! 2nd SW : Initial DC + Capacitive Coupling

Capacitive Coupling Initial DC Conditions

SLIDE 13

20/ 09/ 05 MOS-AK 2005 13

Capacitive Coupling

! Capacitive coupling is stronger to drain than to gate.

Gate Coupling Drain Coupling Gate Coupling Drain Coupling

SLIDE 14

20/ 09/ 05 MOS-AK 2005 14

Key Components (Initial DC Condition)

! 1st SW Initial

! KCL balance between forward and reverse Idiode ! Accumulation Igb is much smaller than forward Idiode

! 2nd SW Initial

! KCL balance between forward Idiode*2 and inversion Igb

1

st SW

1

st SW

Idio,rev Idio,rev Idio,for Idio,for Igb,acc Igb,acc Igb,inv Igb,inv

2nd SW 2nd SW

Idio,for Idio,for

SLIDE 15

20/ 09/ 05 MOS-AK 2005 15

Key Components (AC Coupling)

! Basically a voltage-divider that consists of:

! gate-body capacitance and junction capacitance

! Drain AC coupling is more significant than gate AC coupling

rev j for j acc gb rev j DD bs

C C C C V V

, , , ,

+ + = ∆

Cj,for Cj,for Cj,rev Cj,rev Cgb,acc Cgb,acc VDD VDD

+ ∆Vb

+

∆Vb

SLIDE 16

20/ 09/ 05 MOS-AK 2005 16

Key Components (Body-Effect)

! Body potential is established mostly by diode and gate characteristics (DC & AC). ! This body potential is translated into the actual switching performance by the body-effect (the main transfer function). Vbody

Vt vs. Vbody

Vt & speed

Diode current Gate current Gate capacitance Junction capacitance

SLIDE 17

20/ 09/ 05 MOS-AK 2005 17

Impact of Gate Capacitance & Current

! Cgb is critical for VDD dependence slope ! Igb is a major factor in 130nm technology and below

Increasing inversion Igb 2nd Vb ↑

0.8 1.0 1.2 1.4 1.6

10
5

5 10 15 20 25 30

(1

st-2 nd)/2 nd [%]

VDD [V] Inve r sion I

gb Impac t

Inve r sion C gb Impac t

0.8 1.0 1.2 1.4 1.6

10
5

5 10 15 20 25 30

(1

st-2 nd)/2 nd [%]

VDD [V] Increasing accumulation Cgb 2nd Vb ↓

db sb gb db DD nd b

C C C C V V + + = ∆

2 ,

SLIDE 18

20/ 09/ 05 MOS-AK 2005 18

Impact of Diode Current

! The diode current characteristic is the key characteristic dominating the VDD and temperature dependences of the history-effect:

! Proportional to forward Idiode ! Inversely proportional to reverse Idiode Increasing forward Idiode 1st Vb ↓↓ 2nd Vb ↓ F

r

war d I

diode L

e ve l Impac t

0.8 1.0 1.2 1.4 1.6

10
5

5 10 15 20 25 30

(1

st-2 nd)/2 nd [%]

VDD [V] Re ve r se I

diode Impac t

0.8 1.0 1.2 1.4 1.6

10
5

5 10 15 20 25 30

(1

st-2 nd)/2 nd [%]

VDD [V] Increasing reverse Idiode 1st Vb ↑

SLIDE 19

20/ 09/ 05 MOS-AK 2005 19

Outline

! Bulk CMOS vs. PD-SOI CMOS ! Self-heating ! Floating-Body Modeling: History-Effect

! Definition ! Underlying Physics ! Key Components & Their Impacts

! Parameter Extraction Flow ! Challenges in Measurement & Extraction ! Tied-Body Modeling

! History–Effect in Tied-Body CMOS ! Parasitic Gate Capacitance ! Distributed Body Resistance

! Conclusion

SLIDE 20

20/ 09/ 05 MOS-AK 2005 20

Do History-Effect Modeling First!

! Intrinsic MOSFET characteristics has only small impact on history effect.

Intr insic MOSF E T

Charac te ristic s I

Dsat, I

ff, Vt, …

Par asitic

Charac te ristic s I

dio de, I g b, …

History E ffe c t

SLIDE 21

20/ 09/ 05 MOS-AK 2005 21

PD-SOI Parameter Extraction Procedure

Body- E ffe c t & Cg F

itting Ve ry Crude IV F itting

Body Cur r e nts F

itting (I

dio de, I g b, e tc )

Che c k

History E ffe c t

Re fine All IV F itting

Tied Body Floating Body

SLIDE 22

20/ 09/ 05 MOS-AK 2005 22

Challenges in Measurement & Extraction

Ac tive Ga te Po ly P+ I / I ST I P+ N+ P+ P- P w/ halo

Parasitic Opposite Type Gate Neck Easily Gets Fully-Depleted

SLIDE 23

20/ 09/ 05 MOS-AK 2005 23

Parasitic Opposite-Type Gate

! Big discrepancy in Igb characteristic due to the parasitic

! Especially in inversion region

! Need a bulk wafer

1.5
1.0
0.5

0.0 0.5 1.0 1.5 10

14

10

13

10

12

10

11

1x10

10

1x10

9

1x10

8

1x10

7

1x10

6

Bulk BT/SOI IGG IGB

Gate Current [A] VG [V]

pMOS

1.5
1.0
0.5

0.0 0.5 1.0 1.5 10

14

10

13

10

12

10

11

1x10

10

1x10

9

1x10

8

1x10

7

1x10

6

Bulk BT/SOI IGG IGB

Gate Current [A] VG [V]

nMOS

SLIDE 24

20/ 09/ 05 MOS-AK 2005 24

Fully-Depleted Neck

! Low-doping neck can cause artifacts in measured data

0.6
0.4
0.2

0.0 0.2 0.4 0.6 0.0 0.1 0.2 0.3 0.4 0.5

VDS=1.2V VDS=0.1V nMOSFET 2/0.0875µm

VT [V] Vbs [V] Body- E ffe c t

1.0
0.5

0.0 0.5 0.0 0.5 1.0 1.5

CJunction [pF] Vbias [V] Junc tion Capac itanc e

SLIDE 25

20/ 09/ 05 MOS-AK 2005 25

Back-Bias Range of Interest

! Sometimes the body effect is not able to fit for the entire range. ! Then some range should be compromised. ! Separating TB and FB models maybe more desirable.

T ie d Body & Bulk F loating Body

0.6
0.4
0.2

0.0 0.2 0.4 0.6 0.0 0.1 0.2 0.3 0.4 0.5

VDS=1.2V VDS=0.1V nMOSFET 2/0.0875µm

VT [V] Vbs [V]

Re ve r se F

r

war d

SLIDE 26

20/ 09/ 05 MOS-AK 2005 26

Outline

! Bulk CMOS vs. PD-SOI CMOS ! Self-heating ! Floating-Body Modeling: History-Effect

! Definition ! Underlying Physics ! Key Components & Their Impacts

! Parameter Extraction Flow ! Challenges in Measurement & Extraction ! Tied-Body Modeling

! History–Effect in Tied-Body CMOS ! Parasitic Gate Capacitance ! Distributed Body Resistance

! Conclusion

SLIDE 27

20/ 09/ 05 MOS-AK 2005 27

Can Body Be Really Tied?

! Tied-body PD-SOI circuit experiences the coupling effects exactly same as floating-body one. ! Thus it exhibits history effect too.

0.0 0.1 0.2 0.3 0.4 0.5

0.3
0.2
0.1

0.0 0.1 0.2 0.3

Vbody [V] Time [nsec] Body Pote ntial F luc tuation

Gate Coupling Drain Coupling Body RC Decay 10

8

10

9

10

4 8 12

WN=WP/2=1µm

(1

st-2 nd)/2 nd [%]

Frequency [Hz] Histor y E ffe c t of T ie d- Body CMOS

SLIDE 28

20/ 09/ 05 MOS-AK 2005 28

BSIM-SOI: Gate Capacitance

Ac tive Ga te Po ly P+ I / I Drain So urc e Bo dy

An+ Ap+

Physic al

Drain So urc e Bo dy

BSIM- SOI

Ag bc p

Rbodyext Rbp n+/ p n+/ p- p+/ p- Rbodyext Rbp n+/ p n+/ p- p+/ p-

Rbodyext Rbp n+/ p n+/ p n+/ p Rbodyext Rbp n+/ p n+/ p n+/ p

SLIDE 29

20/ 09/ 05 MOS-AK 2005 29

1 2 3

3
2
1

VG [ V] CGG

BSIM-SOI: Gate Capacitance

∫

⋅ ≈

T FB

V V GS G GB

dV C Q

N+ gate P body P+ gate P body

Gate Capac itanc e

Ac tive Ga te Po ly P+ I / I ST I P+ N+ P+ P- P w/ halo

∫

⋅ ≈

DD T

V V GS G GC

dV C Q

Over- Estimated

SLIDE 30

20/ 09/ 05 MOS-AK 2005 30

BSIM-SOI: Gate Capacitance

10

8

10

9

10

6 7 8 9

WN=WP/2=1µm 10 FET Segments Physical Agbcp=An++Ap+ Agbcp=An+ Agbcp=An++Ap+/3

Delay (1

st+2 nd)/2 [ps/stage]

Frequency [Hz]

Impac t on Switc hing De lay

1 2 3 10 20 30 40 Qp+ Qn+ Qp+/Qn+ Ratio

VG [V] QGC

0.0 0.2 0.4 0.6 0.8

Qp+/Qn+

Char ge Ratio

~4.5%

! The charge ratio is 0.2~0.5 within practical range

! 2 ~ 5x overestimation

! Its impact of switching delay is not negligible

SLIDE 31

20/ 09/ 05 MOS-AK 2005 31

BSIM-SOI: Distributed Body Resistance

Single L umpe d Distr ibute d

Rbodyext RbpH/N n+/ p

FET

n+/ p-

cap

p+/ p-

cap

n+/ p

FET

RbpH/N N segments Rbodyext Rbp

Mode l Me asur e me nt

DC Values AC Values?

SLIDE 32

20/ 09/ 05 MOS-AK 2005 32

BSIM-SOI: Distributed Body Resistance

10

8

10

9

10

2 4 6 8 10

WN =WP/2 =5µm WN =WP/2 =1µm Agbcp=An++Ap+/3 Physical 1-Lump Scale=1.0 1-Lump Scale=1/3 1-Lump Scale=0.1

(1

st-2 nd)/2 nd [%]

Frequency [Hz] R ule of T humb

! Factor of 1/3 for single-side contact; 1/12 for double-side contact ! Mathematically derived for gate resistance noise

!

R. P. Jinal, IEEE T-ED, pp. 1505-1509, October 1984

! Applicable for other distributed resistance associated with active gain

10

8

10

9

10

2 4 6 8 10

WN =WP/2 =5µm WN =WP/2 =1µm Agbcp=An++Ap+/3 Rbodyext=10KΩ Physical 1-Lump Scale=1.0 1-Lump Scale=1/3 1-Lump Scale=1/12

(1

st-2 nd)/2 nd [%]

Frequency [Hz] Double - Side (H- Gate ) Single - Side (T

Gate )

SLIDE 33

20/ 09/ 05 MOS-AK 2005 33

Conclusion

! Self-heating is poorly modeled in general and worsens the convergence ! History-effect is one of the major difficulties in floating-body PD- SOI parameter extraction