Cache-Timing Attacks
Matteo BOCCHI System Research & Applications STMicroelectronics S.r.l. 2018/12/06
Cache-Timing Attacks Matteo BOCCHI System Research & - - PowerPoint PPT Presentation
Cache-Timing Attacks Matteo BOCCHI System Research & Applications STMicroelectronics S.r.l. 2018/12/06 Agenda 2 STM32 Nucleo Boards STM32 Firewall Cache-Timing Attack Evict&Time vs. MbedTLS AES on STM32
Matteo BOCCHI System Research & Applications STMicroelectronics S.r.l. 2018/12/06
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3 Ultra-low-power Mainstream
Cortex-M0 Cortex-M0+ Cortex-M3 Cortex-M4 Cortex-M7
High-performance Wireless
Note : Cortex-M0+ Radio Co-processor
TM
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microprocessors
hardware to program/debug
connect to companion chips boards
Arduino UNO extension connectors easy access to add-
Integrated Debugging and programming probe Morpho extension headers: Direct access to all STM32 I/Os STM32 Microcontroller Flexible board power supply through USB or external source
complete product range from ultra-low power to high-performance
(*) thanks to the electrical compatibility it can be used as a shield for Arduino UNO R3 or similar
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monitoring each access from the AHB masters to the Flash memory or SRAM1 AHB slaves
software interacting with OEM code.
protected code outside of a protected area.
user code execution.
Application benefits
CORTEX- M4 DMA AHB BUS MATRIX SRAM1 Flash memory FIREWALL
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Call Gate Entry Protected Code Execution Execution Complete? NO Clear Intermediate Variables and CPU registers Call Gate Exit YES
TRUSTED EXECUTION Example Code Execution FIREWALL CLOSED FIREWALL OPEN FIREWALL CLOSED CALL GATE EXIT GATE
Closed Open Idle
FIREWALL IDLE
Unprotected Code Unprotected Code
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it could be implemented using just logical and arithmetic operations
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lookup tables (hardcoded) or compute them during system initialization
done (𝑙 key, 𝑜 plaintext)
slower when 𝑜 13 = 147)
machine, that the overall AES time is maximum when 𝑙 13 ⊕ 𝑜 13 = 8
⊕ 𝑜 13 = 8 ⊕ 𝑜 13 𝑙 13 ⊕ 𝑜 13 ⊕ 𝑜 13 = 8 ⊕ 147 𝑙 13 = 8 ⊕ 147 𝑙 13 = 155
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NUCLEO-L476RG SERIAL PORT TERMINAL 115.200 bit/s 8-N-1
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Last-Level-Cache:
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The attacker: 1. Clears (flush) a specific cache section 2. Launches/observes victim’s process 3. Checks new cache status, measuring time to access those memory addresses
step-by-step (if the victim’s process is long and complex)
some observations more
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1. Empty the cache (flush) 2. Launch victim’s process 3. Check new cache status
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flush(probe[i]); service_encrypt(plaintext, ciphertext, service_ctx); size_t time = rdtsc(); maccess(probe[i]); size_t delta = rdtsc() - time; if (delta > MIN_CACHE_MISS_CYCLES) { /* cache miss */ }
Attacker’s code
Bytes Look-Up Tables Sbox
Victim’s OpenSSL-based “secure” service 1 2 3
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flush_reload_RELEASE.tar.gz
/* attacker’s and victim’s source code */
/* OpenSSL source code */
/* Step-by-step HowTo */
the victim
Flush+Reload attacks flushing the portion of cache used by a certain table
caused shorter timings
last-round key
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Any questions?
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Contact: matteo.bocchi@st.com