C B + k i 1 / i i , 1 i n , i ( 2 1 ) - - PDF document

c b k i 1 i i 1 i n i 2 1 can be used to block t i
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C B + k i 1 / i i , 1 i n , i ( 2 1 ) - - PDF document

Priority Inheritance Protocol Midterm Grades 96 100 Let the blocker task inherit the priority of 90 80 79 the task being blocked 80 70 critical section 60 Grade P(1) only blocked by 4 50 40 27 1 1 1 30 20 Inherit


slide-1
SLIDE 1

Chenyang Lu CSE 467S 1

Midterm Grades

79 80 27 96

10 20 30 40 50 60 70 80 90 100 1 3 5 7 9 11 13 15

Grade

Mean = 71; Std = 19.

Chenyang Lu CSE 467S 2

Priority Inheritance Protocol

  • Let the blocker task “inherit” the priority of

the task being blocked

1 4 4 4

2 4 6 8 10 12 14 16 18 20 22

1 1 critical section

P(1) only blocked by 4

Inherit priority 1!

2 3 4

return to priority 4!

Chenyang Lu CSE 467S 3

Priority Inheritance Protocol

  • When a task Ti is blocked on a semaphore:
  • prio(i) task Tk holding the semaphore if prio(Tk) is lower

than prio(i)

  • When Tk release a semaphore:
  • If Tk does not block any other processes, it returns to its
  • riginal (e.g., RMS) priority
  • If Tk still blocks other processes, it inherits the highest

priority among the blocked processes.

  • Priority Inheritance is transitive
  • T2 blocks T1 and inherits prio(T1)
  • T3 blocks T2 and inherits priority Prio(T1)

Chenyang Lu CSE 467S 4

PIP Analysis Assumptions

  • RMS scheduling and assumptions
  • All process run on single CPU.
  • All processes are periodic
  • Zero context switch time.
  • Deadline = Period
  • All semaphores are binary
  • All semaphores are properly nested

Chenyang Lu CSE 467S 5

Bounded Number of Blocking

  • Task Ti can be blocked by at most

min(m,n) times

  • m: the number of distinct semaphores that

can be used to block Ti

  • n: the number of lower-priority tasks that

can block Ti

Chenyang Lu CSE 467S 6

Schedulability Analysis

  • A set of n periodic tasks using PIP can be

scheduled by RMS if

  • All tasks are ordered by priorities (T1 has the

highest priority)

  • Bi: the maximum time that task Ti can be

blocked by lower-priority tasks.

=

− ≤ + ≤ ≤ ∀

i k i i i k k

i T B T C n i i

1 / 1

) 1 2 ( , 1 ,

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SLIDE 2

Chenyang Lu CSE 467S 7

Compute Bi

/* potential blocking by other jobs */ B1=0; for each Tj with priority lower than Ti {

b1 = longest critical section in Tj that can block Ti B1 = B1 + b1

} /* potential blocking by semaphores */ B2=0; for each semaphore Sk that can block Ti {

b2 = longest critical section guarded by Sk in lower priority tasks B2 = B2 + b2

} Return min(B1, B2)

Chenyang Lu CSE 467S 8

Priority Ceiling

  • Priority ceiling C(Sk) of a semaphore Sk
  • Highest priority among tasks requesting Sk.
  • A critical region guarded by Sk may lock

a task Ti only if C(Sk) ≥ Ti’s priority

Chenyang Lu CSE 467S 9

Priority Ceiling Protocol

  • Priority ceiling of system: The highest priority ceiling

among resources currently in use

  • A task can acquire a resource only if
  • the resource is free, AND
  • it has a higher priority than the priority ceiling of the

system

  • Improvements from PIP:
  • Guarantees there is no deadlock
  • Each task is blocked for at most the duration of ONE

critical section

  • Downside: more run-time overhead than PIP

Chenyang Lu CSE 467S 10

Scheduling Review

Optimality No blocking Deadline = Period context switch time = 0 Periodic Single CPU Assumptions X √ √ √ Fixed priority X √ √ √ DMS √ √ √ No Dynamic Priority Fixed Priority √ X √ √ √ √ √ √ √ RMS/PIP EDF RMS

Chenyang Lu CSE 467S 11

Context-switching time

  • In practice, OS context switch
  • verhead is small.
  • Non-zero context switch time can push

limits of a tight schedule.

  • Leave margin in your schedule.
  • Techniques exist to reduce number of

context switches.

Chenyang Lu CSE 467S 12

Fixing scheduling problems

  • Change periods in requirements.
  • Reduce execution times of tasks.
  • Reduce blocking factors.
  • Get a faster CPU.
  • Multi-processor systems.
  • Replace with software components with

hardware (ASIC, FPGA) components

slide-3
SLIDE 3

Chenyang Lu CSE 467S 13

Multi-processor system

  • Tight coupling among processors
  • E.g., Dual-processor Sun workstations
  • Communicate through shared memory and on-

board buses

  • Scheduled by a common scheduler/OS
  • Global scheduling
  • Partitioned scheduling
  • States of all processors available to each
  • ther

Chenyang Lu CSE 467S 14

Distributed system

  • Loose coupling among processors
  • Each processor has its own scheduler
  • Costly to acquire states of other processors
  • Broad range of systems
  • Processor boards mounted on a VME bus
  • Automobile: hundreds of processors connected

through a Control Area Network (CAN)

  • Air traffic control system on a wide area network

Chenyang Lu CSE 467S 15

End-to-End Task Model

  • An (end-to-end) task is composed of multiple

subtasks running on multiple processors

  • Message
  • Event
  • Remote method invocation
  • Subtasks are subject to precedence

constraints

  • Task = a chain/tree/graph of subtasks

Chenyang Lu CSE 467S 16

Notation

  • Ti = {Ti,1, Ti,2, … , Ti,n(i)}
  • n(i): the number of subtasks of Ti
  • Precedence constraint: Job Ji,j cannot

be released until Ji,j-1 is completed.

Chenyang Lu CSE 467S 17

End-to-End Deadline

  • A task is subject to an end-to-end

deadline

  • Does not care about the response time of a

particular subtask

  • How to guarantee end-to-end deadlines
  • n a distributed system?

Chenyang Lu CSE 467S 18

End-to-End Scheduling Framework

1. Task allocation: bind tasks to processors 2. Synchronization protocol: enforce precedence constraints 3. Subdeadline assignment 4. Schedulability analysis

slide-4
SLIDE 4

Chenyang Lu CSE 467S 19

Task Allocation

  • Load code (e.g., objects) to processors
  • Strategies
  • Offline, static allocation
  • Allocate a task when it arrives
  • Re-allocate (migrate) a task after it starts
  • NP-hard: heuristics needed

Chenyang Lu CSE 467S 20

Bin-packing formulation

  • Pack subtasks to bins (processors) with

limited capacity

  • Size of a subtask Ti,j: ui,j = ei,j/pi
  • Capacity of each bin is its utilization bound
  • e.g., 0.69 (RMS) or 1 (EDF) under certain assumptions
  • Goal: minimize the number of bins subject to the

capacity constraints

  • Ignore communication cost
  • Assume every subtask is periodic

Chenyang Lu CSE 467S 21

Bin-Packing Heuristics: First- Fit

  • Subtasks assigned in arbitrary order
  • To allocate a new subtask Ti,j
  • If Ti,j can be added to an existing processor Pl

(1≤l≤k) without exceeding its capacity, allocate Ti,j to Pk

  • Else add a new processor Pk+1 and allocate Ti,j to it.

Chenyang Lu CSE 467S 22

Performance limit of First-Fit

  • Number of processors needed: m/m0 -> 1.7 as

m0 -> ∞

  • m: number of processors needed under First-Fit
  • m0: minimum number of processors needed
  • First-Fit can always find a feasible allocation
  • n m processors if total subtask utilization is

no greater than m(21/2-1) = 0.414m

  • Assuming fixed-priority scheduling, identical

processors