Bounded Radius Routing Perform bounded PRIM algorithm Under = 0, - - PowerPoint PPT Presentation

bounded radius routing
SMART_READER_LITE
LIVE PREVIEW

Bounded Radius Routing Perform bounded PRIM algorithm Under = 0, - - PowerPoint PPT Presentation

Bounded Radius Routing Perform bounded PRIM algorithm Under = 0, = 0.5, and = Compare radius and wirelength Radius = 12 for this net Practical Problems in VLSI Physical Design Bounded Radius Routing (1/16) BPRIM Under


slide-1
SLIDE 1

Practical Problems in VLSI Physical Design Bounded Radius Routing (1/16)

Bounded Radius Routing

Perform bounded PRIM algorithm

Under ε = 0, ε = 0.5, and ε = ∞ Compare radius and wirelength Radius = 12 for this net

slide-2
SLIDE 2

Practical Problems in VLSI Physical Design Bounded Radius Routing (2/16)

BPRIM Under ε = 0

Example

Edges connecting to nearest neighbors = (c,d) and (c,e)

  • We choose (c,d) based on lexicographical order

s-to-d path length along T = 12+5 > 12 (= radius bound) First appropriate edge found = (s,d)

slide-3
SLIDE 3

Practical Problems in VLSI Physical Design Bounded Radius Routing (3/16)

BPRIM Under ε = 0 (cont)

Radius bound = 12

edges connecting to nearest neighbors s-to-y path length along T ties broken lexicographically should be ≤ 12;

  • therwise

appropriate used first feasible appr-edge

slide-4
SLIDE 4

Practical Problems in VLSI Physical Design Bounded Radius Routing (4/16)

BPRIM Under ε = 0 (cont)

slide-5
SLIDE 5

Practical Problems in VLSI Physical Design Bounded Radius Routing (5/16)

BPRIM Under ε = 0 (cont)

slide-6
SLIDE 6

Practical Problems in VLSI Physical Design Bounded Radius Routing (6/16)

BPRIM Under ε = 0.5

Radius bound = 18

edges connecting to nearest neighbors s-to-y path length along T ties broken lexicographically should be ≤ 18;

  • therwise

appropriate used first feasible appr-edge should be ≤ 12

slide-7
SLIDE 7

Practical Problems in VLSI Physical Design Bounded Radius Routing (7/16)

BPRIM Under ε = 0.5 (cont)

slide-8
SLIDE 8

Practical Problems in VLSI Physical Design Bounded Radius Routing (8/16)

BPRIM Under ε = 0.5 (cont)

slide-9
SLIDE 9

Practical Problems in VLSI Physical Design Bounded Radius Routing (9/16)

BPRIM Under ε = ∞

Radius bound = ∞ = regular PRIM

slide-10
SLIDE 10

Practical Problems in VLSI Physical Design Bounded Radius Routing (10/16)

BPRIM Under ε = ∞ (cont)

slide-11
SLIDE 11

Practical Problems in VLSI Physical Design Bounded Radius Routing (11/16)

Comparison

As the bound increases (12 → 18 → ∞)

Radius value increases (12 →17 → 22) Wirelength decreases (56 → 49 → 36)

slide-12
SLIDE 12

Practical Problems in VLSI Physical Design Bounded Radius Routing (12/16)

Bounded Radius Bounded Cost

Perform BRBC under ε = 0.5

ε defines both radius and wirelength bound Perform DFS on rooted-MST Node ordering L = {s, a, b, c, e, f, e, g, e, c, d, h, d, c, b, a, s} We start with Q = MST

slide-13
SLIDE 13

Practical Problems in VLSI Physical Design Bounded Radius Routing (13/16)

MST Augmentation

Example: visit a via (s,a)

Running total of the length of visited edges, S = 5 Rectilinear distance between source and a, dist(s,a) = 5 We see that ε · dist(s,a) = 0.5 · 5 < S Thus, we reset S and add (s,a) to Q (note (s,a) is already in Q)

slide-14
SLIDE 14

Practical Problems in VLSI Physical Design Bounded Radius Routing (14/16)

MST Augmentation (cont)

dotted edges are added visit nodes based on L

slide-15
SLIDE 15

Practical Problems in VLSI Physical Design Bounded Radius Routing (15/16)

Last Step: SPT Computation

Compute rooted shortest path tree on augmented Q

slide-16
SLIDE 16

Practical Problems in VLSI Physical Design Bounded Radius Routing (16/16)

BPRIM vs BRBC

Under the same ε = 0.5

BPRIM: radius = 18, wirelength = 49 BRBC: radius = 12, wirelength = 52 BRBC: significantly shorter radius at slight wirelength increase