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Block Diagram of Level 1 Pattern Pixel Track Vertex Recognition - - PowerPoint PPT Presentation
Block Diagram of Level 1 Pattern Pixel Track Vertex Recognition - - PowerPoint PPT Presentation
Block Diagram of Level 1 Pattern Pixel Track Vertex Recognition System Reconstruction Reconstruction FPGA DSP Associative Vertex Farm Memory (1 DSP per crossing) DSP Track Farm Average Average (4 DSPs per crossing) Latency:
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1 1
Pixel System
FPGA Associative Memory
Pattern Recognition Track Reconstruction Vertex Reconstruction
DSP Track Farm (4 DSPs per crossing)
Average Latency: 0.4 µs Average Latency: 200 µs
DSP Vertex Farm (1 DSP per crossing)
Average Latency: 250 µs Average latency for the Level 1 trigger: 0.5 ms Number of DSPs (e.g. TMS320C6701): 2000 + 500 = 2500
Block Diagram of Level 1
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BTeV Pixel Trigger (FPGA)
- Form Hit Clusters, sort by quadrant (More Parallel)
- Search “In out” and “Out in” in precision bend view
- Start near pipe and near edge – Use Beam/Material constraints
- Find Confirming hit, then match non-bend pixels
- Pass on info to DSP’s
Approach reduces combinatorics too Inside Hole Of Next plane Outside, but close, and from beam Fake Hit Fake Plane
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DSP’s Form tracks form segments found by FPGA’s
BTeV Pixel Trigger (DSP Part A)
Tracking 85% efficient > 5GeV
- BTeVGEANT contains hadronic
interactions, γ conversions, δ-rays
- Pixel hits have non-Gaussian tails
(derived from test beam data) After clean up cuts Momentum of tracks in fiducial
- Average of 2 interactions per
crossing Tracks get passed to Vertex DSP
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74%
1%
BTeV Pixel Trigger (DSP Part B)
- Form Verticies
- Require 2 tracks:
a) Within 2mm of primary b) > 6 “errors” of impact Keep ~50% of B’s Reject 99% of min bias
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L1 Trigger Performance
State efficiency(%) state efficiency(%) B → π+π- 63 Bo → K+π- 63 Bs → DsK 71 Bo → J/ψ Ks 50 B-→ DoK- 70 Bs → J/ψK* 68 B-→ Ksπ- 27 Bo → ρoπo 56
Full GEANT simulations including pattern
recognition done for trigger
Refinements and Recoveries in Level 2 and Level 3
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Pixel hits after 1st segment finding
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