BIST at ICT?! ?!!?!?!?!?!?!?!?!?!?!?!? The view at 10,000 feet - - PowerPoint PPT Presentation

BIST at ICT?!

The view at 10,000 feet

John Malian, Cisco Systems, Inc.

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Agenda

Background Benefits Current Method Deployed Projects Challenges Future Considerations

Background

There is a growing need for internal test structures inside our ASICs

Content addressable memory (CAM) for example, may require a “brute force” method of testing all cells, which may take hours in a CPU access test. BIST reduces test time to seconds

BIST via JTAG available on many Cisco ASICs

Number of devices increasing

Need a correlation between chip level testing and system level testing

Background - Key Members

Structural Test

• Kevin Nguyen
• Eo Trinh
• Steve Lee
• John Malian

ASIC Test ASIC DFT

• Jaclyn Dang
• Han Ta
• Trung Pham
• Matthias Kamm
• Lap Le
• Zoe Conroy
• Bill Eklow

We still have a lot of work to do, but without their expertise we would have not gotten this far

Benefits

Running BIST at In-Circuit Test allows for easier ASIC replacement of bad components

System is not fully assembled (heat sinks, chassis, trays) Possible need for external thermal management

Added level of coverage before functional test

Capability of testing portions of ASIC cores At-speed testing of key IO signals and memory busses

Possible benefits

Power/GND coverage – not direct failure, but assumed

Current Development Flow

Set Up Macros Debug and Verify Generate SVF Debug and Verify Convert SVF to PCF

Asset Scanworks In-Circuit Test System

Deploy to CM Observe Results

Note: Biased to Asset and Agilent

Current Method – Manufacturing Flow

Previous Test Processes In-Circuit Test with BIST

PASS F A I L

ASSET Debug Repair or Replace Functional Test

Deployed Projects

Paradise – MBIST, PRBS* internal/external 1G/2G/4G Uros – MBIST, DC LBIST, AC LBIST, PRBS internal and external 2G/4G Luke – AC LBIST Pixar – LBIST, MBIST

*PRBS: Pseudorandom Binary Sequence

Deployed Projects - Paradise

SFP Loopbacks

Deployed Projects – Uros

Thermal Management SFP Loopbacks

Challenges

Is the test really working? Diagnosis capability JTAG vs. Functional Access Voltage and/or Temperature variance? Thermal management How to control noise in the fixture? Do we have enough juice? Timing

Challenges: Is the Test Really Working?

Challenges

Traditional ICT relies on fault insertion for test effectiveness Getting a BIST test to pass has a “false” sense of security Most BIST tests are internal only

Possible Solution

Use a socketed board and known bad parts from vendor Make sure bad parts failed at nominal temperature/speed

Challenges: Diagnosis

SVF patterns do not carry diagnostic information

Internal BIST tests at in-circuit test can utilize a go/no-go test as the only method of repair is ASIC replacement

External BIST tests have more challenges:

How to pinpoint a defect at the pin level?

Challenges: JTAG vs. Functional Access

Confusion over test passing in-circuit test and failing functional Need to make sure that BIST tests executed at the functional level (i.e. PCI access, for example) match with 1149.1 accessible BIST tests.

If not possible – then document these limitations

Challenges: Temperature/Voltage Variations

Example:

ATE Part is tested on 93k at 7% voltage/temperature margin In-Circuit Test Temp control at in-circuit test very difficult to impossible Voltage trim depends on board design – some products at 3% Functional Test Temperature control in a chamber Voltage trim still dependent on board design

Challenges: Thermal Management

Blocks with Thermal interface pads

Challenges: Thermal Management

front back

Challenges: Noise Inside the Test Fixture

In-circuit test fixtures are noisy!

Adequate for the most part on static-state signals, but might not be adequate for high-speed switching

Dual-stage fixturing has helped in alleviating all seen issues

Only probe necessary signals for BIST tests Power/GND, JTAG TAP, discharge

Wireless fixtures might mitigate some issues related to crosstalk

Still have to contend with a noisy testhead

Challenges: Current Considerations

Concerns over current requirements on BIST tests We have not seen an issue so far

Does not mean it will not be an issue

Clean power delivery is important

Challenges: Timing

Some BIST tests will require external clocks – on board or off-board

External modules might be required

Some BIST tests are dependent on TCK speeds

Future Considerations

Standardization of programming language?

Maybe some sort of high level macro language?

Any other methods of generating vectors?

WGL to PCF? Diagnosis Capability

Q and A