Available Processes Process Name Process Feature C18A6 0.18 CMOS - - PowerPoint PPT Presentation

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C ircuits M ulti- P rojets Technology Processes & Runs in 2015 MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble - France CMP annual users meeting, 4 Feb. 2016, PARIS Available Processes Process Name Process

SLIDE 1

CMP annual users meeting, 4 Feb. 2016, PARIS

CircuitsMulti-Projets

MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble - France

Technology Processes & Runs in 2015

SLIDE 2

Available Processes

CMP annual users meeting, 4 Feb. 2016, PARIS 2

Process Name Process Feature C18A6 0.18µ CMOS H18A6 0.18µ HV-CMOS C35B4C2 0.35µ CMOS 3.3V C35B4C3 0.35µ CMOS 3.3V / 5.0V C35B4O1 0.35µ CMOS-Opto S35D4M5 0.35µ SiGe BiCMOS C35B4M3 0.35µ CMOS-RF H35B4D3 0.35µ HV-CMOS BYE / BYQ 0.8µ BiCMOS (available on request)

SLIDE 3

Process (0.35µ CMOS)

CMP annual users meeting, 4 Feb. 2016, PARIS 3

CMOS 0.35 µ C35 (C35B4C3)

 2 Layers Polysilicon, 4 Layers Metal, 3.3V / 5.0V, High Resistive Poly.  3.3V / 5.0V I/O pads.  Peripheral cells with high driving capability (from 1mA to 24mA)  Application : Analog, Digital, Mixed A/D, RF.  Density : 18 kgates/mm2  Gate Delay: 100ps (NAND2 typical)  Libraries : Digital and Analog Standard Cells + Pads + P-Cells.  CORELIB qualified for 1.8V / 2.2V / 2.7V / 3.3V  CORELIB_V5 qualified for 2.0V / 3.0V / 4.0V / 5.0V

Thick Metal and MIM available in C35B4M3.

4 MPW runs scheduled in 2016.
MPW Price : 650 Euro/mm2

SLIDE 4

CMOS-Opto 0.35µ

CMP annual users meeting, 4 Feb. 2016, PARIS 4

CMOS-Opto 0.35 µ (C35B4O1)

Planarization and anti-reflective coating allows better optical features.
P-Epi wafers for lowering current leakage in the diode (lower dark current).

metal3 via2 metal2 via1 metal1 contact

P+ P- Fox P+ P- n- n+ P- substrate Anti reflective coating PHOTO_DIODE

via3 metal4

P- Epi

Design-kit compatible with the 4 layers metal process option C35B4.
Every C35 MPW run planned by CMP includes the CMOS-Opto option.
4 MPW runs scheduled in 2016.
MPW Price : 810 Euro/mm2

SLIDE 5

Process (0.35µ SiGe)

CMP annual users meeting, 4 Feb. 2016, PARIS 5

SiGe HBT-BiCMOS 0.35 µ S35D4M5

4 Layers Polysilicon / 4 Layers Metal.
Power supply voltage range (2.5V – 3.6V / 5.5V)
Vertical SiGe-HBT NPN : Ft = 70 GHz
High Resistive Polysilicon.
Poly1/Poly2 capacitors
MIM capacitors
Thick Top Metal
4 MPW runs scheduled in 2016.
MPW Price : 890 Euro/mm2

SLIDE 6

Process (0.35µ HV-CMOS)

CMP annual users meeting, 4 Feb. 2016, PARIS 6

HV CMOS 0.35 µ H35 (H35B4D3)

2 Layers Polysilicon, 4 Layers Metal, High Resistive Poly, Thick 4th Metal.
20V / 50 V / 120 V Maximum operating voltage.
3.3V / 5.0V / 20V Maximum gate voltage.
Ron = 0.11 Ohm mm2 for HV-NMOS
Ron = 0.29 Ohm mm2 for HV-PMOS

NMOS50 (50V) PMOS50 (50V) NMOS120 (120V) PMOS120 (120V) NMOSI50 (50V) VERTN1 Standard 3.3V / 5V Isolated 3.3V / 5V

4 MPW runs scheduled in 2016.
MPW Price : 1’000 Euro/mm2

SLIDE 7

0.18µ CMOS & High-Voltage CMOS

CMP annual users meeting, 4 Feb. 2016, PARIS 7

CMOS technology with ≤ 3 mask level adders for HV
Three gate oxides available: 1.8, 5V and 20V
6 metal levels (last metal: 4 µm Al power metal)
Full set of 20 V and 50 V LDMOS devices
Low Rdson
< 14 m*mm2@30 V BVDSS
< 130 m*mm2@70 V BVDSS
1.8 V and 5 V floating logic (N/PFET)
High-voltage vertical NPN & PNP bipolar transistors
Isolated JFET
High-voltage VN capacitors (20-50V)
High voltage well based resistors
1 kV, 2 kV and 4 kV HBM ESD protection structures
OTP (Efuse)
Tool for safe operating area check (SOAC)
4 MPW runs scheduled in 2016.
MPW Price : 1’200 Euro/mm2

SLIDE 8

C18/H18 Devices Key Facts

CMP annual users meeting, 4 Feb. 2016, PARIS 8

Resistors N+ diffusion resistor 72  / □ P+ diffusion resistor 105  / □ TaN resistor 61  / □ N+ poly resistor 370  / □ P+ poly resistor 260  / □ hires poly resistor 1600  / □ Precision poly resistor 165  / □ HV Nwell resistor 3074  / □ HV Pwell resistor 725  / □ Capacitors Single MIM capacitor 2.05 fF / µm² Single MIM HD capacitor 2.7 fF / µm² Dual MIM capacitor 4.1 fF / µm² Dual MIM HD capacitor 5.4 fF / µm² HiK MIM capacitor 4.1 fF / µm² VN capacitor 0.1-0.7 fF / µm² HV VN capacitor 0.1-0.5 fF / µm²

LV fets LV fets in HV well HV asymmetric fets in HV wells HV symmetric fets (nfet in Substrate) Vds Vgs 1.8V 5.0V 1.8V 5.0V 20V** 50V 20V 50V 1.8V (3.5nm) nfet* / pfet* Nfethvt / pfethvt nfeti* / pfeti* Nfetihvt / pfetihvt nfeti20t pfet20t nfeti50t pfet50t 5.0V (12nm) nfetm pfetm nfetim pfetim nfet20mh nfeti25m pfet25m nfeti50m pfet50m 20V (52nm) nfeti20h pfet20h nfeti50h pfet50h nfet20hs pfet20hs nfet50hs pfet50hs

* RF layout available ** 25V Vds for nfeti25m,pfeti25m

SLIDE 9

Runs in 2015

CMP annual users meeting, 4 Feb. 2016, PARIS 9

Number of prototypes in 2015 : 83 (74 in 2014) Number of Low volume prod. in 2015 : 25 (11 in 2014) 29 scheduled MPW runs (31 in 2014) 1 extra run (Production) (1 in 2014) 37 circuits CMOS 44.5% (63.5% in 2014)

(47 in 2014)

22 circuits SiGe 26.5% (20% in 2014)

(15 in 2014)

24 circuits HV-CMOS 29% (16.5% in 2014)

(12 in 2014)

CMOS SiGe HV-CMOS

2015

CMOS SiGe HV-CMOS

2014

SLIDE 10

Runs Histogram

CMP annual users meeting, 4 Feb. 2016, PARIS 10

50 100 150 200 250

1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015

Prototypes Productions

SLIDE 11

DRIE trench dicing at

CMP annual users meeting, 4 Feb. 2016, PARIS 11

Cross-sections: Width = 15µm, depth = 200µm

Trench 30um from edge: 90°/ 253µm

(Courtesy AMS) (Courtesy AMS)

SLIDE 12

DRIE trench dicing at , cont‘d

CMP annual users meeting, 4 Feb. 2016, PARIS 12

Trench

(Courtesy AMS)

Trench

Trench dicing available on request (one additional mask)

SLIDE 13

CMOS-Opto BARC – C35B4OA

CMP annual users meeting, 4 Feb. 2016, PARIS 13

CMOS-Opto 0.35µm with Bottom Anti-Reflective Coating (BARC) (C35B4OA)

Bottom Anti-Reflective Coating allows better sensitivity than ARC.
P-Epi wafers for lowering current leakage in the diode (lower dark current).

Cross-section of a photo-diode (BARC process option)

Available from CMP at any of the 4 MPW runs in 2016.
Contact CMP for pricing.

SLIDE 14

TSV processes at

CMP annual users meeting, 4 Feb. 2016, PARIS 14

TSV on a single chip for backside bumping Face2back two tiers stack. TSV on top tier’s front side

TSV post-processing available on dedicated engineering runs.
UBM, RDL, and Bumping available on top of PADTSV.

SLIDE 15

Conclusion

CMP annual users meeting, 4 Feb. 2016, PARIS 15

Rich process portfolio : CMOS, CMOS-Opto, CMOS-RF, SiGe, HV-CMOS, …
4 MPW runs for all processes in 2016.
Available specific process options :

 DRIE trench dicing  New enhanced CMOS-Opto with BARC (C35B4OA)  TSV : for single chip backside bumping  TSV : Face2back two tiers stacking

Continuing the strong partnership and collaboration CMP / ams

http://cmp.imag.fr