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Authenticache: Harnessing Cache ECC for System Authentication Anys - - PowerPoint PPT Presentation

Aug 16, 2022 318 likes •1.11k views

Authenticache: Harnessing Cache ECC for System Authentication Anys Bacha and Radu Teodorescu Department of Computer Science and Engineering The Ohio State University http://arch.cse.ohio-state.edu Security and Everyday Computing Security is

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SLIDE 1

Authenticache: Harnessing Cache ECC for System Authentication

Anys Bacha and Radu Teodorescu Department of Computer Science and Engineering The Ohio State University http://arch.cse.ohio-state.edu

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SLIDE 2

Anys Bacha

Security and Everyday Computing

Authenticache: Harnessing Cache ECC for System Authentication 2

Security is now crucial to all computing markets, especially with the advent of IoT

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SLIDE 3

Anys Bacha

Security Challenges

Authenticache: Harnessing Cache ECC for System Authentication 3

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SLIDE 4

Anys Bacha

Security Challenges

Authenticache: Harnessing Cache ECC for System Authentication 3

  • Password management
  • Complexity due to different accounts having policies
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SLIDE 5

Anys Bacha

Security Challenges

Authenticache: Harnessing Cache ECC for System Authentication 3

  • Password management
  • Complexity due to different accounts having policies
  • Secure key storage
  • Increases complexity for low cost IoT devices
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SLIDE 6

Anys Bacha

Security Challenges

Authenticache: Harnessing Cache ECC for System Authentication 3

  • Password management
  • Complexity due to different accounts having policies
  • Software as a Service
  • Personal device at workplace increasing security risks
  • Secure key storage
  • Increases complexity for low cost IoT devices
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SLIDE 7

Anys Bacha

Physical Unclonable Functions (PUF)

Authenticache: Harnessing Cache ECC for System Authentication 4

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SLIDE 8

Anys Bacha

Physical Unclonable Functions (PUF)

Authenticache: Harnessing Cache ECC for System Authentication 5

Chip

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SLIDE 9

Anys Bacha

Physical Unclonable Functions (PUF)

Authenticache: Harnessing Cache ECC for System Authentication 5 Slow transistors Fast transistors

Chip

  • Exploit randomness in silicon
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SLIDE 10

Anys Bacha

Physical Unclonable Functions (PUF)

Authenticache: Harnessing Cache ECC for System Authentication 6

Chip Silicon Fingerprints

  • Systematic outputs unique to device
  • Exploit randomness in silicon
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SLIDE 11

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 7

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SLIDE 12

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 8

Enrollment

Silicon Fingerprints

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SLIDE 13

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 8

…

00010

Enrollment

Silicon Fingerprints

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SLIDE 14

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 8

…

00010 11001 …

Enrollment

Silicon Fingerprints

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SLIDE 15

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 9

… …

Enrollment

Challenge

01100 00110

Response

… …

00010 11001 Silicon Fingerprints

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SLIDE 16

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 10

… …

Enrollment

Challenge

01100 00110

Response

… …

00010 11001

Authentication

Challenge

01100 00110

Response

… …

00010 11001

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SLIDE 17

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 10

… …

Enrollment

Challenge

01100 00110

Response

… …

00010 11001

Authentication

Challenge

01100 00110

Response

… …

00010 11001

  • Auth. Request
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SLIDE 18

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 11

… …

Enrollment

Challenge

01100 00110

Response

… …

00010 11001

Authentication

Challenge

01100 00110

Response

… …

00010 11001

…

01100

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SLIDE 19

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 11

… …

Enrollment

Challenge

01100 00110

Response

… …

00010 11001

Authentication

Challenge

01100 00110

Response

… …

00010 11001

…

01100 00110 …

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SLIDE 20

Anys Bacha

PUF System Authentication

Authenticache: Harnessing Cache ECC for System Authentication 11

… …

Enrollment

Challenge

01100 00110

Response

… …

00010 11001

Authentication

Challenge

01100 00110

Response

… …

00010 11001

…

01100 00110 …

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SLIDE 21

Anys Bacha

Related Work

Authenticache: Harnessing Cache ECC for System Authentication 12

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SLIDE 22

Anys Bacha

Related Work

Authenticache: Harnessing Cache ECC for System Authentication 12

Aribiter PUF

  • Arbiter PUF (Lee et al. VLSI’04)
  • Signal traversing maze of cascaded switch

blocks

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SLIDE 23

Anys Bacha

Related Work

Authenticache: Harnessing Cache ECC for System Authentication 12

Aribiter PUF

  • Arbiter PUF (Lee et al. VLSI’04)
  • Signal traversing maze of cascaded switch

blocks

Ring Oscillator PUF

  • Ring Oscillator PUF (Suh et al. DAC’07)
  • Delay loops feeding oscillations into counters
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SLIDE 24

Anys Bacha

Related Work

Authenticache: Harnessing Cache ECC for System Authentication 12

Aribiter PUF

  • Arbiter PUF (Lee et al. VLSI’04)
  • Signal traversing maze of cascaded switch

blocks

SRAM PUF

  • SRAM PUF (Guajardo et al. CHES’07)
  • Power-on states of 6T SRAM cell

Ring Oscillator PUF

  • Ring Oscillator PUF (Suh et al. DAC’07)
  • Delay loops feeding oscillations into counters
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SLIDE 25

Anys Bacha

Related Work

Authenticache: Harnessing Cache ECC for System Authentication 12

Aribiter PUF

  • Arbiter PUF (Lee et al. VLSI’04)
  • Signal traversing maze of cascaded switch

blocks

SRAM PUF

  • SRAM PUF (Guajardo et al. CHES’07)
  • Power-on states of 6T SRAM cell

Ring Oscillator PUF

  • Ring Oscillator PUF (Suh et al. DAC’07)
  • Delay loops feeding oscillations into counters

Authenticache: No custom hardware On-chip error correction logic in processor caches

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SLIDE 26

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 13

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SLIDE 27

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 14

  • Caches optimized for density
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SLIDE 28

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 14

  • Caches optimized for density
  • Sensitive to process variation
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SLIDE 29

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 14

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 30

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 15

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 31

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 15

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 32

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 15

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 33

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 15

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines

Repeatable

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 34

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 15

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines

Repeatable

L2 L2 L2 L2 L2 L2 L2 L2

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 35

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 16

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines Error Count Cache Line Address

1 2 3 4 5

Repeatable

L2 L2 L2 L2 L2 L2 L2 L2

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 36

Anys Bacha

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 16

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines Error Count Cache Line Address

1 2 3 4 5

Repeatable

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 37

Anys Bacha

1 2 3 4 5

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 17

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines Error Count Cache Line Address

<1 overlap/cache Repeatable

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 38

Anys Bacha

1 2 3 4 5

Cache Errors as Silicon Fingerprints

Authenticache: Harnessing Cache ECC for System Authentication 17

20 40 60 80 100 120

  • 10
  • 20
  • 30
  • 40
  • 50
  • 60

Relative Correctable Error Range (mV) Cache Lines Error Count Cache Line Address

<1 overlap/cache Unique Repeatable

  • Caches optimized for density
  • Sensitive to process variation
  • Itanium processor 8 L2 caches

Intel 9560 Processor

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SLIDE 39

Anys Bacha

The Authenticache System

Authenticache: Harnessing Cache ECC for System Authentication 18

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SLIDE 40

Anys Bacha

The Authenticache System

Authenticache: Harnessing Cache ECC for System Authentication 18

way 0 way 1 way n set 0 way 0 way 1 way n set j … … … way 0 way 1 way n set 1 way 0 way 1 way n set j+1 … … … way 0 way 1 way n set k way 0 way 1 way n set m … … …

Cache Layout

  • Exploit process variation in

LLC for randomness

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SLIDE 41

Anys Bacha

The Authenticache System

Authenticache: Harnessing Cache ECC for System Authentication 18

way 0 way 1 way n set 0 way 0 way 1 way n set j … … … way 0 way 1 way n set 1 way 0 way 1 way n set j+1 … … … way 0 way 1 way n set k way 0 way 1 way n set m … … …

Cache Layout Error Map x y

1 1 1 1 1 1 1

Vi

  • Exploit process variation in

LLC for randomness

  • Construct cache maps as a

function of voltage and correctable errors

slide-42
SLIDE 42

Anys Bacha

The Authenticache System

Authenticache: Harnessing Cache ECC for System Authentication 19

way 0 way 1 way n set 0 way 0 way 1 way n set j … … … way 0 way 1 way n set 1 way 0 way 1 way n set j+1 … … … way 0 way 1 way n set k way 0 way 1 way n set m … … …

Cache Layout Error Map x y

1 1 1 1 1 1 1

Vi

  • Exploit process variation in

LLC for randomness

  • Construct cache maps as a

function of voltage and correctable errors

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

z

Vj Vk

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SLIDE 43

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 20

e e e e e e

Error Map

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SLIDE 44

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 20

𝐷ℎ𝑏𝑚𝑚𝑓𝑜𝑕𝑓 = 𝑦1, 𝑧1, 𝑊

1 , (𝑦2, 𝑧2, 𝑊 2)

e e e e e e

A B Error Map

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SLIDE 45

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 20

𝐷ℎ𝑏𝑚𝑚𝑓𝑜𝑕𝑓 = 𝑦1, 𝑧1, 𝑊

1 , (𝑦2, 𝑧2, 𝑊 2)

B e e e e e e (x2,y2) A (x1,y1)

A B Error Map

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SLIDE 46

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 20

𝐷ℎ𝑏𝑚𝑚𝑓𝑜𝑕𝑓 = 𝑦1, 𝑧1, 𝑊

1 , (𝑦2, 𝑧2, 𝑊 2)

B e e e e e e (x2,y2) A (x1,y1)

A B Error Map V1 = V2

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SLIDE 47

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 21

𝐷ℎ𝑏𝑚𝑚𝑓𝑜𝑕𝑓 = 𝑦1, 𝑧1, 𝑊

1 , (𝑦2, 𝑧2, 𝑊 2)

B e e e e e e (x2,y2) A (x1,y1)

A B 𝑆𝑓𝑡𝑞𝑝𝑜𝑡𝑓 = 0, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) < 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐) 1, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) ≥ 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐)

Manhattan Distance

Error Map V1 = V2

slide-48
SLIDE 48

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 21

𝐷ℎ𝑏𝑚𝑚𝑓𝑜𝑕𝑓 = 𝑦1, 𝑧1, 𝑊

1 , (𝑦2, 𝑧2, 𝑊 2)

B e e e e e e (x2,y2) A (x1,y1)

A B 𝑆𝑓𝑡𝑞𝑝𝑜𝑡𝑓 = 0, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) < 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐) 1, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) ≥ 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐)

Manhattan Distance

Error Map V1 = V2

dist(A,e)=5

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SLIDE 49

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 21

𝐷ℎ𝑏𝑚𝑚𝑓𝑜𝑕𝑓 = 𝑦1, 𝑧1, 𝑊

1 , (𝑦2, 𝑧2, 𝑊 2)

B e e e e e e (x2,y2) A (x1,y1)

A B 𝑆𝑓𝑡𝑞𝑝𝑜𝑡𝑓 = 0, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) < 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐) 1, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) ≥ 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐)

dist(B,e)=4

Manhattan Distance

Error Map V1 = V2

dist(A,e)=5

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SLIDE 50

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 21

𝐷ℎ𝑏𝑚𝑚𝑓𝑜𝑕𝑓 = 𝑦1, 𝑧1, 𝑊

1 , (𝑦2, 𝑧2, 𝑊 2)

B e e e e e e (x2,y2) A (x1,y1)

A B 𝑆𝑓𝑡𝑞𝑝𝑜𝑡𝑓 = 0, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) < 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐) 1, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) ≥ 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐)

dist(B,e)=4

5 > 4

Manhattan Distance

Error Map V1 = V2

dist(A,e)=5

slide-51
SLIDE 51

Anys Bacha

Challenge and Response

Authenticache: Harnessing Cache ECC for System Authentication 21

𝐷ℎ𝑏𝑚𝑚𝑓𝑜𝑕𝑓 = 𝑦1, 𝑧1, 𝑊

1 , (𝑦2, 𝑧2, 𝑊 2)

B e e e e e e (x2,y2) A (x1,y1)

A B 𝑆𝑓𝑡𝑞𝑝𝑜𝑡𝑓 = 0, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) < 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐) 1, 𝑒𝑗𝑡𝑢(𝐵, 𝑓𝑏) ≥ 𝑒𝑗𝑡𝑢(𝐶, 𝑓𝑐)

dist(B,e)=4

5 > 4

Manhattan Distance

Error Map V1 = V2

1

dist(A,e)=5

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SLIDE 52

Anys Bacha

Experimental Framework

Authenticache: Harnessing Cache ECC for System Authentication 22

  • System:
  • BL860c-i4 Integrity Server from HP
  • 2x 9560 Itanium II CPUs
  • Prototype in System Firmware
  • Thermal experiments through power virus
  • Monte Carlo simulations
  • Different cache sizes
  • Different error maps and noise profiles

VR Adapt Voltage System Firmware (SMM) Operating System Vdd Request Self-test Cache

Event Test

Voltage Control Error Handler

ECC Cache Line

Authentication Algorithm

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SLIDE 53

Anys Bacha

Identification and Noise

Authenticache: Harnessing Cache ECC for System Authentication 23 Code Distance (bits)

0.01 0.02 0.03 0.04 0.05 0.06 64 128 192 256 320 384 448 512 Inter-chip

Identification in presence of environmental and measurement noise

slide-54
SLIDE 54

Anys Bacha

Identification and Noise

Authenticache: Harnessing Cache ECC for System Authentication 24 Code Distance (bits)

0.01 0.02 0.03 0.04 0.05 0.06 64 128 192 256 320 384 448 512 Intra-chip (10% Noise) Inter-chip

Identification in presence of environmental and measurement noise

slide-55
SLIDE 55

Anys Bacha

Identification and Noise

Authenticache: Harnessing Cache ECC for System Authentication 25 Code Distance (bits)

0.01 0.02 0.03 0.04 0.05 0.06 64 128 192 256 320 384 448 512 Intra-chip (10% Noise) Intra-chip (150% Noise) Inter-chip

Identification in presence of environmental and measurement noise

slide-56
SLIDE 56

Anys Bacha

Identification and Noise

Authenticache: Harnessing Cache ECC for System Authentication 25 Code Distance (bits)

0.01 0.02 0.03 0.04 0.05 0.06 64 128 192 256 320 384 448 512 Intra-chip (10% Noise) Intra-chip (150% Noise) Inter-chip

Misidentification

Identification in presence of environmental and measurement noise

slide-57
SLIDE 57

Anys Bacha

Identification and Noise

Authenticache: Harnessing Cache ECC for System Authentication 25 Code Distance (bits)

0.01 0.02 0.03 0.04 0.05 0.06 64 128 192 256 320 384 448 512 Intra-chip (10% Noise) Intra-chip (150% Noise) Inter-chip

< 2 ppm Misidentification

Identification in presence of environmental and measurement noise

slide-58
SLIDE 58

Anys Bacha

Identification and Noise

Authenticache: Harnessing Cache ECC for System Authentication 25 Code Distance (bits)

0.01 0.02 0.03 0.04 0.05 0.06 64 128 192 256 320 384 448 512 Intra-chip (10% Noise) Intra-chip (150% Noise) Inter-chip

< 2 ppm << 1 ppm Misidentification

Identification in presence of environmental and measurement noise

slide-59
SLIDE 59

Anys Bacha

Identification and Noise

Authenticache: Harnessing Cache ECC for System Authentication 25 Code Distance (bits)

0.01 0.02 0.03 0.04 0.05 0.06 64 128 192 256 320 384 448 512 Intra-chip (10% Noise) Intra-chip (150% Noise) Inter-chip

< 2 ppm << 1 ppm Misidentification

Observe 6% intra-chip variation after +25° C

slide-60
SLIDE 60

Anys Bacha

Resiliency to Noise

Authenticache: Harnessing Cache ECC for System Authentication 26

20 40 60 80 100 120 140 160 64-bit 128-bit 256-bit 512-bit Expected Errors Removed Unexpected Errors Injected

CRP Size Max Tolerable Noise (%)

slide-61
SLIDE 61

Anys Bacha

Resiliency to Noise

Authenticache: Harnessing Cache ECC for System Authentication 26

20 40 60 80 100 120 140 160 64-bit 128-bit 256-bit 512-bit Expected Errors Removed Unexpected Errors Injected

CRP Size Max Tolerable Noise (%)

Enrollment Phase

slide-62
SLIDE 62

Anys Bacha

Resiliency to Noise

Authenticache: Harnessing Cache ECC for System Authentication 26

20 40 60 80 100 120 140 160 64-bit 128-bit 256-bit 512-bit Expected Errors Removed Unexpected Errors Injected

CRP Size Max Tolerable Noise (%)

Enrollment Phase

12% 62%

slide-63
SLIDE 63

Anys Bacha

Resiliency to Noise

Authenticache: Harnessing Cache ECC for System Authentication 26

20 40 60 80 100 120 140 160 64-bit 128-bit 256-bit 512-bit Expected Errors Removed Unexpected Errors Injected

CRP Size Max Tolerable Noise (%)

Enrollment Phase Environmental Conditions

12% 62%

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SLIDE 64

Anys Bacha

Resiliency to Noise

Authenticache: Harnessing Cache ECC for System Authentication 26

20 40 60 80 100 120 140 160 64-bit 128-bit 256-bit 512-bit Expected Errors Removed Unexpected Errors Injected

CRP Size Max Tolerable Noise (%)

Enrollment Phase Environmental Conditions

12% 14% 62% 142%

slide-65
SLIDE 65

Anys Bacha

Repeatability and Performance

Authenticache: Harnessing Cache ECC for System Authentication 27

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SLIDE 66

Anys Bacha

Repeatability and Performance

Authenticache: Harnessing Cache ECC for System Authentication 28

  • Repeatable cache line errors
slide-67
SLIDE 67

Anys Bacha

Repeatability and Performance

Authenticache: Harnessing Cache ECC for System Authentication 28

0.2 0.4 0.6 0.8 1 1 2 3 4 7 8 CDF vs. Number of Cache Line Self-tests

CDF Number of Cache Line Self-tests

  • Repeatable cache line errors
slide-68
SLIDE 68

Anys Bacha

Repeatability and Performance

Authenticache: Harnessing Cache ECC for System Authentication 28

0.2 0.4 0.6 0.8 1 1 2 3 4 7 8 CDF vs. Number of Cache Line Self-tests

CDF Number of Cache Line Self-tests

  • Repeatable cache line errors

CRP ≥ 128-bit

slide-69
SLIDE 69

Anys Bacha

Repeatability and Performance

Authenticache: Harnessing Cache ECC for System Authentication 28

0.2 0.4 0.6 0.8 1 1 2 3 4 7 8 CDF vs. Number of Cache Line Self-tests

CDF Number of Cache Line Self-tests

  • Repeatable cache line errors

CRP ≥ 128-bit All CRP

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SLIDE 70

Anys Bacha

Repeatability and Performance

Authenticache: Harnessing Cache ECC for System Authentication 28

0.2 0.4 0.6 0.8 1 1 2 3 4 7 8 CDF vs. Number of Cache Line Self-tests

CDF Number of Cache Line Self-tests

  • Repeatable cache line errors

50 100 150 200 250 64-bit 128-bit 256-bit 512-bit 1 Attempt 2 Attempts 4 Attempts 8 Attempts

CRP Size Time (ms)

CRP ≥ 128-bit All CRP

  • Linear increase in runtime as a

function of self-test attempts

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SLIDE 71

Anys Bacha

Model Building Attack Case Study

Authenticache: Harnessing Cache ECC for System Authentication 29

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SLIDE 72

Anys Bacha

Model Building Attack Case Study

Authenticache: Harnessing Cache ECC for System Authentication 29

0.4 0.5 0.6 0.7 0.8 0.9 1 Prediction Rate vs. Observed CRP 50000 100000 150000 200000 250000 300000 350000 400000

Prediction Rate (bits/response) CRP Count

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SLIDE 73

Anys Bacha

Model Building Attack Case Study

Authenticache: Harnessing Cache ECC for System Authentication 29

0.4 0.5 0.6 0.7 0.8 0.9 1 Prediction Rate vs. Observed CRP 50000 100000 150000 200000 250000 300000 350000 400000

Prediction Rate (bits/response) CRP Count

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SLIDE 74

Anys Bacha

Model Building Attack Case Study

Authenticache: Harnessing Cache ECC for System Authentication 29

0.4 0.5 0.6 0.7 0.8 0.9 1 Prediction Rate vs. Observed CRP 50000 100000 150000 200000 250000 300000 350000 400000

Prediction Rate (bits/response) CRP Count

10% Noise

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SLIDE 75

Anys Bacha

Model Building Attack Case Study

Authenticache: Harnessing Cache ECC for System Authentication 29

0.4 0.5 0.6 0.7 0.8 0.9 1 Prediction Rate vs. Observed CRP 50000 100000 150000 200000 250000 300000 350000 400000

Prediction Rate (bits/response) CRP Count

Regenerate logical error map

10% Noise

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Anys Bacha

  • Observe that correctable errors in caches can be used as silicon

fingerprints

  • Introduce a challenge-response design that can sustain large

number of authentications (10 year lifetime)

  • Demonstrate robustness of technique to noise (up to 142%)
  • Realize a proof-of-concept to show system is practical

Conclusion

Authenticache: Harnessing Cache ECC for System Authentication 30

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SLIDE 77

Anys Bacha

Thank you! Questions?

Authenticache: Harnessing Cache ECC for System Authentication 31

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SLIDE 78

Authenticache: Harnessing Cache ECC for System Authentication

Anys Bacha and Radu Teodorescu Department of Computer Science and Engineering The Ohio State University http://arch.cse.ohio-state.edu