Audit of the BLM LHC system Beam loss interface to machine - - PowerPoint PPT Presentation

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Audit of the BLM LHC system Beam loss interface to machine - - PowerPoint PPT Presentation

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Audit of the BLM LHC system Beam loss interface to machine protection and energy distribution The BLECS combiner and survey card Functional test bench for the BLECF and BLECS Jonathan Emery 10 June 2008 1 Audit of the BLM LHC system Beam

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SLIDE 1

Audit of the BLM LHC system

Beam loss interface to machine protection and energy distribution The BLECS combiner and survey card Functional test bench for the BLECF and BLECS

Jonathan Emery 10 June 2008

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SLIDE 2

Audit of the BLM LHC system

Beam loss interface to machine protection and energy distribution

Jonathan Emery 10 June 2008

2

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SLIDE 3

Outline

Overview Beam permit hardware Beam permit check Beam energy

3 Audit of the BLM LHC system

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Overview for one IP

  • The BLM receive the energy through a redundant link from the

CISV

  • The beam permit signals, maskable and unmaskable, are send to

the CIBUS with 2 redundant lines (A and B)

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BLM System CIBUS Unmaskable CISV

Timing network A B

A B Beam info CIBUS Maskable A B Beam info

Interlock network

Audit of the BLM LHC system

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SLIDE 5

Beam permit signal path

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BLECS U CIBUS Maskable

Interlock network

BLETC N°1 BLETC N°16 BLETC N°2 U M M UA M Last BLECS U BLETC N°1 BLETC N°16 BLETC N°2 U M M U M UB MA MB UA UB MA MB CIBUS Unmaskable U UBI MBI BLETC Processing and threshold comparison

Maskable beam permit Unmaskable beam permit

CH 1 CH 16 U M

Measurement from the tunnel Unmaskable Beam Info Maskable Beam Info

Daisy chain from TC1 to BLECS Daisy chain from BLECS1 to CIBUS

Measurements Beam permit processing

Crate 1

3 to 4 crates per IP

Audit of the BLM LHC system

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SLIDE 6

Beam permit daisy chain principle

  • The FPGA provide a clock line to the
  • ne-shot chip
  • The CLR input is used to combine the

signal from the previous card

  • A pull-down resistor is used in case of a

broken wire or a unwanted board removal

  • Same principle for the 2 links

Inside the crate (BLETC to BLETC) Between the crates (BLECS to BLECS)

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FPGA

2MHz Retrig IN

Retriggerable

  • ne-shot

CLR

„1‟

FPGA

2MHz Retrig IN CLR

Card 1 Card 2 to card 3

R

Beam permit line Audit of the BLM LHC system

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SLIDE 7

Beam dump request time stamping

  • A counter starts when the beam permit goes down, stops when the PM freeze

trigger arrives. The CPU calculate the time stamp with the PM freeze arrival time and this counter (1 s accuracy).

  • A status tells is the beam info had arrived after a dump request and gives the

delay between this 2 events.

7

BLETC

  • r

BLECS CIBUS BOBR

Turn counter Bunch counter Counter dump to beam info Counter dump to PM freeze Beam permit

Clk Clk Trig Freeze Start Beam info Beam permit

BLECS

Audit of the BLM LHC system

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SLIDE 8

Beam permit test procedure1

  • Tests the beam permit lines (BPL) inside the crate
  • Tests the BPL between the crates (on the same IP)
  • Test results are saved in the database

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BLECS U BLETC N°1 BLETC N°16 BLETC N°2 U M M M Last BLECS CIBUS U All lines to „FALSE‟

Energy link

last BLECS had received the last dump request and notify all the other BLECS

1 2 3

Send the card number which have to provoke the dump and U or M The BLECS provoke the dump which is transmitted to the last BLECS before the CIBUS

Audit of the BLM LHC system

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SLIDE 9

Control of the BPL by an outside system only if the BLM system is in “test mode” The BLM system can only go to “test mode” if the beam info is “False” Only one line (A or B) can be “True”. The other one stay “False”

Tests the BPL from the last crate to the CIBUS 1. Request from outside system (interlock system) to enter in test 2. BLM system waits for the beam info to be „False‟ (U & M) Enter in the test mode after a predefined time 3. Then it is possible to force only one BPL (A or B) to „true‟ 4. The BLM system return to normal state when the result is given to the BLECS The beam permits goes to normal operation state only if the test is successful

9 Audit of the BLM LHC system

Beam permit test procedure 2 (proposal)

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Beam energy

  • The beam energy arrives from the timing system to the CISV located on the
  • ne crate of each IP (blmr)
  • The CISV distribute the energy to all BLECS of the point (3 to 4 crates) in

parallel through the cables between the crates.

  • The integrity of the link is continuously checked and errors are counted and

saved in the logging database.

  • Conversion is done from 16bits to 5bits levels (32 levels of the BLM system).

This conversion (linear) is hardcoded inside the FPGA of the BLECS

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Last BLECS CISV

Timing network A B

BLETC N°1 BLETC N°16 BLETC N°2

A B

BLECS BLETC N°1 BLETC N°16 BLETC N°2

A B A B

Audit of the BLM LHC system

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SLIDE 11

Beam energy link

  • New energy value every 100ms
  • The energy frames are transmitted every ms

(the energy value is repeated between new values)

  • Uses a serial link, 1MHz bit rate, Manchester encoding
  • The frame is 32 bits long and content:

LHC energy header (“1001“) Spare bits (”000”) Toggle bit expected to have a transition every 100ms Energy value (16 bits) CRC (8 bits)

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BLECS CISV

Timing network A B

BLETC N°1 BLETC N°16 BLETC N°2

A B Error counters to the DB

Audit of the BLM LHC system

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SLIDE 12

Audit of the BLM LHC system

The BLECS combiner and survey card

Jonathan Emery 10 June 2008

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Outline

Hardware Crate overview Beam energy Beam permit High voltage control Voltages survey Tests

13 Audit of the BLM LHC system

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Hardware

  • Based on DAB card

=> VME 64x => Stratix 40k => SRAM memory => One site code update => Specific BI signals on P0

  • Reuse of existing material

=> FPGA code for VME Serial number chip Flash memory => Flash programming

14 Audit of the BLM LHC system

  • Beam permit

=> Daisy chain between crates => Beam Interlock CIBUS interface

  • Interface to high voltage PS

DAC for control ADC for monitoring

  • Monitoring VME PS

for specific behavior (ripples)

  • Crate interconnections for

test of the BLM system

Combiner features added

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Hardware

IC Ionization chamber BLECF Tunnel card for acquisition BLETC Processing card BLECS Combiner card CIBUS Interlock interface HV High Voltage power supply

Interconnection between crates (1 to 4) Beam permit: same connection between BLECS than between BLECS and CIBUS Last BLECS (before the CIBUS) control the HV but all can read the monitoring of this voltage. Beam energy distribution from last crate to all the others

15 Audit of the BLM LHC system

IC

BLECF BLECS

CIBUS Unmaskable Beam Permit

BLETC N°1 BLETC N°16 BLECF

Create 1

BLECS BLETC N°1 BLETC N°16

Create 2

Last BLECS BLETC N°1 BLETC N°16

Create n CIBUS Maskable Beam Permit HV1 + HV2

BLECF BLECF BLECF BLECF

IC IC IC IC IC

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Crate overview

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High voltage BLECS BLETC N°1 CPU CIBUS BOBR BLETC N°16 CISV BLETC N°8 BLETC N°9

„1‟

Daisy chain of the beam permit lines (U and M) Energy 16 bits Turn clk Energy 5 bits to all BLETC Acquisition and control Beam permit Beam info Control Monitoring + info

Audit of the BLM LHC system

Triggers

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SLIDE 17

Beam energy

Serial reception with redundant channels (A and B) Continuous check for: Frame reception, CRC error, timeout frame, time out toggle bit Translation 16 bits to 5bits+1bit(error signal). Hardcoded conversion table Substitution of the original value by any value (in test mode only) Additional information on the reminded free bits Serial transmission to the 16 TC receivers in parallel

CRC error or timeout A CRC error or timeout B Toggle bit timeout source used for the energy Action Comment A

  • Normal operation

1 B Increase counter CRC error A 1 A Increase counter CRC error B 1 1

  • Previous beam energy value used

x x 1 Highest Energy “FFFF” & error bit „1‟ Increase counter Toggle bit timeout The timeout is 110% of the normal time between the energy values

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P0 Connector P2 Connector Beam Energy (Serial) Beam Energy (Serial) FPGA Energy conversion & add information CISV

16 BLETC

Audit of the BLM LHC system

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Beam Energy (0 to 31) [5 bits] Error bit [1 bit] SofResetTC [1bit] System under Test Unmaskable Beam Info [1 bits] Maskable Beam Info [1 bits] BPL Unmaskable test activation [1 bit] BPL Maskable test activation [1 bit] Beam Permit Line test TC Card Number [4 bits] Bit position [15..11] [10] [9] [8] [7] [6] [5] [4] [3..0] Broken link state* 31 (highest) 1 1 1 CISV transmission specification

  • 1. LHC energy header => "1001“
  • 2. ”000”
  • 3. Toggle bit
  • 4. Energy value (16 bits)
  • 5. CRC (8 bits)

Energy value (16 bits) CRC check (errors counter) Toggle bit time out check (errors counter) BLECS transmission specification

  • 1. ”10010000” header (8 bits)
  • 2. Composite data (16 bits)
  • 3. Toggle bit + ”000” (4 bits)
  • 4. CRC (4 bits)

To 16 BLETC in parallel

Beam energy

18 * Applied when both transmission are broken. Audit of the BLM LHC system

Used to provoke beam dump to TC individually (during test) Information from the CIBUS

Conversion + additional information & control

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SLIDE 19

BP control Beam Permit from TC (M) Beam Permit from TC (U) Beam Permit from BLECS (UA) Beam Permit from BLECS (UB) Beam Permit from BLECS (MA) Beam Permit from BLECS (MB) Beam Permit to CIBU (UA) Beam Permit to CIBU (UB) Beam Permit to CIBU (MA) Beam Permit to CIBU (MB) System test result BLECS FPGA

Beam permit

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& &

Audit of the BLM LHC system

„True‟ „False‟ BP control BP control BP control

Control A or B

  • nly when under test

Beam is permitted: „1„ Beam is forbidden: „0„

The beam permit signal is travelling on the VME P0 connector from the first BLETC (1) to the last BLETC (16) and then to the BLECS with a daisy chain link. One for the unmaskable and one for the maskable

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Analog SUM Pot digitally Controlled (8 bits steps) Gmax= 1/100 Gmin=1/500 Modulation Offset From FPGA (SPI) From/to FPGA (I2C) 16 bits DAC8532 RC Filter Zenner 6.8V Close to the connector (P2) BLECS output HV output Voltage step 0.153 mV 45.8 mV Voltage range 6.8 V 2040 V Modulation range peak-peak (theoretical values) 78nV to 200mV 23 V to 60V

High voltage control

20 Audit of the BLM LHC system

Inverter G=2

Ionization chambers high voltage controlled by 0-10V signal Analog sum between the working voltage 5V-6.8V and a small modulation (16mV) High voltage PS

Gain=300

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High voltage monitoring

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High voltage 1 & 2 Voltage & Current

Audit of the BLM LHC system Comparators FPGA ADC

BLECS

BLECS input @ the HV [V] @ the HV [I] ADC maximum resolution (DC) 24 bits 0.6 mV 0.18 mV 1.2 nA Measured noise (over 10h) 1.61 mV 0.5V @ 1505V 40mA @ 1.3mA Comparators LOW HIGH Voltage < 500V > 2100V Current < 0.5mA > 18mA

The high voltage power supplies have analog output monitors to view the voltage and current levels, these signals are digitalized with an ADC. There are also comparators checking the levels.

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Low voltage monitoring

22 Audit of the BLM LHC system Comparators FPGA

BLECS

Digitalization comparator 5V (VME) 3V3 (VME) ±12V (VME) not used on the board 5V (P0 Analog) 15V (P0 Analog)

  • 15V (P0 Analog)

5V (Reference of the DAC) 10V (HV comparator ref 2x)

The voltages on the combiner are monitored since some ripples due to ageing were observed on previous BLM system. There are 2 ways to observe it:

  • With the comparators connected to counters
  • With ADC values (~5kHz), the FPGA calculate the delta (max – min)

when this value increase, its means there is ripples.

ADC

time U Normal voltage Threshold

Under the threshold value: the comparator notify it, the counter is increasing by one OR the counter is measuring the time below

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SLIDE 23
  • System test includes the most important test below

Consistency, BPTC, HVLF

  • Related to the thresholds and parameters

Consistency Check of the LSA parameters inside the electronic

  • Related to the beam interlock

BPTC Check of the beam dumping capability on each BLETC BPBIS Check of the beam dumping capability of the BLECS to the BIS

  • Related to the high voltage

HVLF Check of the connection from HV to IC to BLETC HVCFC Check of the BLECF capability to add 100pA on all channels (1650) HVRDAC Reset of the BLECF current compensation (related to 10pA test) (1800) HVRGOH Reset of the GOH on the BLECF (optical link to the surface (2000)

23 Audit of the BLM LHC system

Tests

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SLIDE 24

Test “SYSTEM TEST”

  • The “SYSTEM TEST” should be done regularly
  • A timer on the BLECS is requesting this test with 2 level of

priority: Normal and High

  • When the High priority request is raised, at the next dump, the

beam permit lines are forced “False” and a system test should be started and be successful in order to go back to normal state

  • The system test includes the following tests:

Consistency HVLF modulation BPTC (beam permit lines until the last BLECS)

24 Audit of the BLM LHC system

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BLETC Threshold Comparators HV (Vin*300) BLECS Combiner and survey Control 0-6.8V Real excitation signal BLM chamber HV 0-2000V BLECF Current to Frequency Current Optical Link VME SURFACE TUNNEL

Audit of the BLM LHC system

Tests: HVLF (HV modulation)

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All these tests are part of the SYSTEM TEST

Tests request matrix

26 Audit of the BLM LHC system

* The result decision is done externally and is written

  • n the combiner (Passed/Failed) in order to gives the

beam permit again. Internal Timer User Expert Consistency* x x x BPTC Beam Permit Lines x x x HVLF HV Modulation x x x BPBIS* x HVCFC HVRDAC HVRGOH x Manual actions x

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BLECS overview

Links the BLM system to the Interlock system Receives and translates the energy Control the detectors‟ HV Request periodic test Test parts of the BLM system

All BPL except the one to the CIBUS The connections of all the installed detectors (HVLF) Initiate test related to HV level

Blocks the BPL if a test failed

System test, Consistency, BPBIS

27 Audit of the BLM LHC system

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SLIDE 28

Audit of the BLM LHC system

Functional test bench for the BLECF tunnel card and BLECS combiner and survey card

Jonathan Emery 10 June 2008

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SLIDE 29

Outline

BLECF test bench Hardware Software Functional test BLECS test bench Software Functional test Summary

29 Audit of the BLM LHC system

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SLIDE 30

BLECF test bench hardware board

30 Audit of the BLM LHC system

USB module “Quick USB” Power the board from the USB Optical receiver bloc from the BLM mezzanine Current source circuits to feed the BLECF 10pA to 1mA on 8 channels FPGA module (parallax) with custom code including the BLETC processing

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BLECF test bench Lab version Tunnel version

31 Audit of the BLM LHC system

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  • Developed in C with Labwindows/CVI (NI)
  • Can read and decode the frames send from the

BLECF at 100Hz, show it and save it inside a file.

  • Can show and save the result of the BLM processing

which is inside the BLETC.

  • On top of this, the test mode can make the functional

test of the BLECF.

32 Audit of the BLM LHC system

BLECF software presentation

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SLIDE 33

Frame mode Running sums mode

33 Audit of the BLM LHC system

BLECF software presentation

The software takes the complete frames from the BLECF , analyze it and show it. The core processing of the BLM system holds inside the FPGA taken from the BLETC. The software takes the result of it and show it.

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1. 10pA calibration Look at the ADC readings Calculate the exact current The operator correct it on the board Check if there are discontinuity Check if the signal is saturated Save the final value inside a file 2. 1mA calibration Done with a external current source (keithley) The operator correct it on the board Save the final value inside a file 3. Complete test Check the integrity of the optical fiber link Check if the status are working Check the HV level thresholds Check the linearity with internal sources Save everything inside a file

34 Audit of the BLM LHC system

BLECF functional test

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SLIDE 35

Test bench 1

  • Current measurements

at all programming stages

  • Automation of the 2 PS

with Labview: lowering each voltages, look at the status when it changes (comparators thresholds check) and save the result inside a file

35 Audit of the BLM LHC system

BLECS test bench

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SLIDE 36

Test bench 2

  • Use a standard BLM LHC crate
  • Use 2 I/O modules from NI to drive the

BLECS inputs and check the outputs.

  • Gets data from the BLECS with the

CMW wrapper (AB-CO-MA)

36 Audit of the BLM LHC system

BLECS test bench

BLECS

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SLIDE 37

Test bench 1 Test bench 2

37 Audit of the BLM LHC system

BLECS test bench

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BLECF test bench

  • Aim to be used to test 750 boards in

the lab and in the tunnel

  • Ability to test FPGA code
  • Custom test board using commercial

modules

  • Software in Labwindows/CVI
  • Calibration assistance
  • Full automated functional test
  • Saves full measurement into multiples

files

BLECS test bench

  • Aim to test 45 boards
  • Ability to test FPGA code
  • Use commercial input/outputs

modules (analog and digital)

  • Software in Labview
  • Partial automation for complex logic

(all beam permit lines states)

  • Uses status of the FPGA continuous

check for the energy reception, turn clock.

  • Test report on a excel file

38 Audit of the BLM LHC system

Summary

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SLIDE 39

Audit of the BLM LHC system

Additional slides

39

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SLIDE 40

Beam energy conversion

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Receiver A

A B

Receiver B Conversion Receiver A Receiver B

A B

A or B Selection

From CISV To BLETC

Status CRC integrity Frame timeout Toggle bit timeout

Audit of the BLM LHC system

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SLIDE 41

Beam permit

Lines from BLECS (Up) Lines from FPGA (frequency > 1MHz)

41 Audit of the BLM LHC system

User.Permit.A+ User.Permit.A- „A‟ D 1 D 2 R 1 R 2 IC 1 T 2 T 1 R 4 Q Q OFF ON „true‟ „false‟

CIBUS interface Combiner outputs

http://ab-div-bdi-bl-blm.web.cern.ch/ab-div-bdi-bl-blm/Electronics/BLECS_Combiner/BLECS-Schematics/Rev3/BLECS_Combiner_Rev3.pdf

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Commune lines between crate

Open drain lines with dedicated IC: OD1 & OD2

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Line direct FPGA to FPGA (200 Ohm between IO) simulation of OD with pull-up OD3 BLECS BLECS BLECS BLECS

OD1 OD2 OD3

Signalization needed: 1) The system is under test (the last crate keep the beam permit lines low) 2) The last crate has received the beam permit low (See BPTC test) 3) Request 100pA test level 4) Request “Modulation level “ of the HV+ Modulation of the HV

Name OD1 OD2 OD3 Description Normal operation 1 1 1 Beam permit indication from the la combiner before the CIBUS x x OD3 can change to indicate BP is false by the last crate before CIBUS (See BPTC test) System under test (all test except Modulation) 1 x The HV level goes at 100pA when any test starts System under test Request Modulation level and Modulation. x

Audit of the BLM LHC system

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SLIDE 43

BLECS 1

Task : Identify the last crate in the chain (the one which is connected to the CIBU)

Last crate identification

HV crate BLECS 2

VCC

100k

GND

5k

FPGA

If the FPGA input = „1‟ there is no BLECS under. Means there is the CIBU and this is the last BLECS before CIBU.

BLECS 2 BLECS 3 BLECS 4

It see its position

P2.A30 P2.A29

BLECS 1

VCC

100k

GND

5k

FPGA

P2.A30 P2.A29 If the FPGA input = „0‟ there is another BLECS under. Means this is not the last BLECS before CIBU. 43 Audit of the BLM LHC system

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SLIDE 44

Phase & Gain tracking

Store result

Thresholds comparison

16 BLETC

Real Excitation Signal 256 positions (one cycle) NV Memory

Excitation Signal frequency 30mHz or 100mHz Sample per period 256 for the reference and 1Hz samples for the Running maximums (Use the Login) The processing is done sequentially for each channel

VME

RAM 256 Channels (32bits) update every Logging read

44 Audit of the BLM LHC system

RAM 256 Channels x256 positions (one cycle) Monitoring of the HV voltage

Tests: HVLF (HV modulation)

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SLIDE 45

HVLF first results (2007)

Gain StdDev Phase StdDev

In this test, there were two methods working in parallel: Simple and double cross-correlation Further investigations needed to ameliorate, select one of the two and fine pitch the method.

There are only 4 channels connected with a chamber for this test. There can be easily identified them on the result

  • f the measurements below.

45 Audit of the BLM LHC system