Architectures Panayiotis Petrides (*) Pedro Trancoso (*)(**) (**) - - PowerPoint PPT Presentation

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Architectures Panayiotis Petrides (*) Pedro Trancoso (*)(**) (**) - - PowerPoint PPT Presentation

Aug 28, 2022 535 likes •768 views

Heterogeneous- and NUMA-aware Scheduling for Many-Core Architectures Panayiotis Petrides (*) Pedro Trancoso (*)(**) (**) Computer Science and (*) Computer Science Engineering Chalmers Department University of Technology University of Cyprus

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Heterogeneous- and NUMA-aware Scheduling for Many-Core Architectures

Panayiotis Petrides(*) Pedro Trancoso (*)(**)

(*) Computer Science Department University of Cyprus

CASPER: Computer Architecture System Performance Evaluation Research

(**) Computer Science and Engineering Chalmers University of Technology

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SLIDE 2

Outline

  • Motivation
  • Scheduling Policy
  • Experimental Results
  • Conclusions

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SLIDE 3

Motivation

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Dual Core Quad Core Multi-core Array

CMP with10 cores

Many-core Array

CMP with -10s -100s low power cores

Intel SCC

CMP with 48 low power cores

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SLIDE 4

Motivation

  • 1. Distance of Core to the Memory Controller
  • Non Uniform Memory Access
  • 2. Resources of Different Core Frequency
  • 3. Memory Controller Accesses Contention

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SLIDE 5

Motivation

Executing SPEC CPU2006 and NAS Benchmark Suites on Intel SCC

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SLIDE 6

Outline

  • Motivation
  • Scheduling Policy
  • Experimental Results
  • Conclusions

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SLIDE 7

Scheduling Policy – Characterizing Applications

Determine how the distance and core frequency factors influence applications execution Both Frequency and Distance change in a linear way

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Scheduling Policy – Characterizing Applications

System Prerequisites in order to determine factors of influence: Discrete Couples of cores with one factor varying and the other one constant

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SLIDE 9

Scheduling Policy: Implementation

  • In order to determine applications behavior we

monitor their execution

  • Construct at each monitor phase the corresponding

queues of a and b

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SLIDE 10

Scheduling Policy: Implementation

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SLIDE 11

Scheduling Policy: Implementation

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SLIDE 12

Outline

  • Motivation
  • Scheduling Policy
  • Experimental Results
  • Conclusions

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SLIDE 13

Experimental Setup

  • Intel SCC Processor
  • 48-core P54C Core Architecture
  • 4 DDR3 Memory Controllers per 12-cores
  • Linux kernel running at each core
  • Applications from SPEC CPU2006 and NAS

benchmarks (medium working size sets)

  • Povray (compute-bound)
  • Sphinx (Medium memory-bound)
  • Libquantum (High memory-bound)
  • Checkpointing/Resuming using

CryoPID library

  • Migration overhead < 1%

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Management Console PC System FPGA

P C I e

Tile Tile R R Tile R Tile R 0,0 0,3 Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R Tile R 5,0 5,3

System Interface

DIMM DIMM DIMM DIMM MC MC MC MC

P54C

(16K L1) 256KB L2

P54C

(16K L1) 256KB L2

MIU

Traffic Gen MPB Router

Tile

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SLIDE 14

Evaluating Scheduling Policy

Scenario 1: Compute-bound and Memory-bound applications

14 0.0% 20.0% 40.0% 60.0% 80.0% 100.0% 120.0% RND SP RND SP RND SP povray sphinx combined Normalized Execution Time

Scenario 1

Migration 800MHz 533MHz 266MHz

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SLIDE 15

Evaluating Scheduling Policy

Scenario 2: Compute-bound and Memory-bound applications

15 0.0% 20.0% 40.0% 60.0% 80.0% 100.0% 120.0% RND SP RND SP RND SP povray libquantum combined Normalized Execution Time

Scenario 2

Migration 800MHz 533MHz 266MHz

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Evaluating Scheduling Policy

Scenario 3: 1 Compute-bound and 2 Memory-bound applications

16 0.0% 20.0% 40.0% 60.0% 80.0% 100.0% 120.0% RND SP RND SP RND SP RND SP povray libquantum sphinx combined Normalized Execution Time Migration 800MHz 533MHz 266MHz

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Evaluating Scheduling Policy

Scenario 4: 2 Memory-bound applications

17 0.0% 20.0% 40.0% 60.0% 80.0% 100.0% 120.0% RND SP RND SP RND SP sphinx libquantum combined Normalized Execution Time Migration 800MHz 533MHz 266MHz

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Evaluating Scheduling Policy

Scenario 5: 1 Compute-bound application

18 0.0% 20.0% 40.0% 60.0% 80.0% 100.0% 120.0% RND SP RND SP povray combined Normalized Execution Time Migration 800MHz 533MHz 266MHz

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SLIDE 19

Outline

  • Motivation
  • Scheduling Policy
  • Experimental Results
  • Conclusions

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SLIDE 20

Conclusions And Future Work

  • We proposed an online scheduling policy

which addresses application demands and characteristics

  • Implementation on a real many-core

architecture using real workloads

  • Performance Improvement
  • Compute-bound up to 36%
  • Memory-bound up to 15%

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SLIDE 21

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Thank You!

CASPER Group University of Cyprus Computer Architecture, Systems and Performance Evaluation Research Visit us: www.cs.ucy.ac.cy/carch/casper