FuseSoc - cores never been so much fun Olof Kindgren Qamcom - - PowerPoint PPT Presentation

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FuseSoc - cores never been so much fun Olof Kindgren Qamcom - - PowerPoint PPT Presentation

Feb 18, 2023 886 likes •1.06k views

FuseSoc - cores never been so much fun Olof Kindgren Qamcom Research & Technology, FOSSi Foundation Who am I? What is FuseSoc? FuseSoC is a package manager ...and a build tool for HDL What is FuseSoc? FuseSoC is a package manager

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FuseSoc - cores never been so much fun Olof Kindgren Qamcom Research & Technology, FOSSi Foundation

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Who am I?

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What is FuseSoc?

FuseSoC is a package manager… ...and a build tool for HDL

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What is FuseSoc?

FuseSoC is a package manager… ...and a build tool for HDL

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Why use FuseSoc?

Increase portability Reduce maintenance “Focus on your core business, not your cores”

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FuseSoC is

the most used package manager non-intrusive modular extendable resourceful battle-proven

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Case : Target different tools

fusesoc run --target=sim serv

uses default simulator

fusesoc run --target=sim --tool=modelsim serv fusesoc run --target=sim --tool=xsim serv No changes needed. Some tool-specific setting needed

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FuseSoC Edalize

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FuseSoC VUnit CoCoTB ASIC flows? ...

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Kactus2 MyHDL Migen CLaSH IceStudio ... Edalize

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Tomorrow

  • Generators
  • Formal verification
  • Use flags
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Future

  • Librecores integration
  • Edalize everywhere
  • Industry standard - World domination
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Anyone?

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That’s it folks!

https://github.com/olofk/fusesoc http://fusesoc.net https://gitter.im/librecores/fusesoc

Don’t miss...

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Core description files (example)

name : ::picorv32:0-r1 filesets: rtl: files: [picorv32.v] file_type : verilogSource tb: files: [testbench.v] file_type : verilogSource tb_verilator: files: [testbench.cc : {file_type : cppSource}] parameters: firmware: {datatype : file, paramtype : plusarg} COMPRESSED_ISA: datatype : str default : 1 paramtype : vlogdefine targets: default: filesets: [rtl] test: default_tool: icarus filesets: [rtl, tb, "tool_verilator? (tb_verilator)"] parameters: [COMPRESSED_ISA, firmware] toplevel:

  • "tool_verilator? (picorv32_wrapper)"
  • "!tool_verilator? (testbench)"
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supported tools

  • Synthesis/P&R support with icestorm, ise, quartus, trellis, vivado
  • Simulations with ghdl, icarus, isim, modelsim, rivierapro, vcs, verilator, xsim
  • Linting with spyglass, verilator
  • In the works

○ Lattice Diamond, icecube2, radiant ○ ncsim ○ Formal verification with symbiyosys