Architecture Comparison for Concurrent Multi-Band Linear Power - - PowerPoint PPT Presentation

Zhen Zhang, Yifei Li, and Nathan M. Neihart Iowa State University

MWSCAS 2015 – Fort Collins, CO

Architecture Comparison for Concurrent Multi-Band Linear Power Amplifiers

Outline

 Motivation  Theoretical Comparisons

 Efficiency  Linearity  Area

 Conclusions

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Motivation

 Multiband radio is a basic requirement for today’s wireless

devices

 Current 4G standards propose carrier aggregation

 Intra-band and inter-band  Contiguous and non-contiguous

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GSM 850 MHz GSM 1900 MHz

Then

EDGE 800/900 MHz EDGE 1800/1900 MHz UMTS 2100 MHz UMTS 1900 MHz AWS 1700 MHz UMTS 850 MHz UMTS 900 MHz LTE Band 13 LTE Band 17 LTE Band 20 LTE Band 25 Diversity Band 1 Diversity Band 2 Diversity Band 3 Diversity Band 4 GPS Band 1 GPS Band 2 WLAN 2 GHz WLAN 5 GHz

Now

400 MHz 1300 MHz 2200 MHz 3100 MHz 4000 MHz LTE UMTS GSM CDMA-2000 WiFi

iPhone 5 mother board

Motivation

 Current approach consists of packing ever more separate PAs into a

device

 Large area  Complex signal routing  Complex control

 Such architectures do not inherently support simultaneous multi-band

signals

 In light of this, researchers are now beginning to develop

simultaneous multi-band PA architectures

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PA Modules Each IC contains several separate power amplifiers

Motivation

 There are two primary approaches for realizing concurrent

multi-band PAs

 Multiple parallel single-band PAs

 Larger area  Must have some way of combining

the output signals

 Single multi-band PA

 Fewer components  Theoretical drop in efficiency

 Which approach is “better”?

08/05/15 5 IMN OMN

M1 PIN1 @ f1

IMN OMN

M2 PIN2 @ f2

IMN OMN

MM PINM @ fM

+

P01 + P02 + … + P0M

Parallel Single-Band

IMN OMN

M1

+

P01 + P02 + … + P0M

Multiband

PINM @ fM PIN1 @ f1 PIN2 @ f2

Concurrent Multi-Band

Efficiency Comparison

 Drain efficiency is defined as:

𝜽 =

𝑸𝑴 𝑸𝑬𝑫

 Multi-band output power is defined to be the total power in

ALL DESIRED bands 𝑸𝑴 = 𝑸𝒈𝟐 + 𝑸𝒈𝟑

 Assuming a linear device and 2 bands, the drain current is:

𝑱𝑬,𝑸𝑻 = 𝑱𝑬𝑫,𝑵 + 𝒋𝒔𝒈,𝑵𝒅𝒑𝒕 𝟑𝝆𝒈𝑵𝒖 + 𝜾𝑵 𝑱𝑬,𝑵𝑪 = 𝑱𝑬𝑫 + 𝒋𝒔𝒈𝒅𝒑𝒕 𝟑𝝆𝒈𝟐𝒖 + 𝒋𝒔𝒈𝒅𝒑𝒕 𝟑𝝆𝒈𝟑𝒖 + 𝜾

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Single Stage in Parallel Single-Band Concurrent Multiband Load Current Load Current of single stage 𝑄𝑀 – Power delivered to the load 𝑄𝐸𝐷 – Power consumed from the DC supply

Efficiency Comparison

 The drain current swing is fixed

such that 𝟏 ≤ 𝑱𝑬 ≤ 𝟐

 Parallel, single-band architecture

 Class A: 𝑗𝑠𝑔,𝑁 = 0.5 and 𝐽𝐸𝐷 = 0.5  Class B: 𝑗𝑠𝑔,𝑁 = 1 and 𝐽𝐸𝐷 = 0  Class C: 𝑗𝑠𝑔,𝑁 = 1.25 and 𝐽𝐸𝐷 = -0.25

 Single, multi-band architecture

 Numerical methods are used to set 𝑗𝑠𝑔

and 𝐽𝐸𝐷 for each class of operation

 Sweep 𝒈𝟑/𝒈𝟐 from 1 to 10

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1 2 3 4 5 0.5 1 Drain Current (A) 1 2 3 4 5 0.5 1 Drain Current (A) Time (sec)

Parallel Single-band Single Multi-band Class-A 50 % 25 % Class-B 78.5 % 62 % Class-C 82 % 71 % 2-Band Parallel Architecture 2-Band Concurrent Architecture

Efficiency Comparison

 Efficiency can be increased by slightly overdriving the

amplifier

 Non-linear model presented in RF Power Amplifiers for Wireless

Communication by S. Cripps is used for this investigation

 Parallel, single-band architecture  Single, multi-band architecture  𝒘𝒔𝒈 and 𝑾𝑬𝑫 are set such that

𝟏 ≤ 𝑾𝑯 𝒖 ≤ 𝟐

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• 0.5

0.5 1 1.5 0.2 0.4 0.6 0.8 1 Normalized Input Voltage (V) Normalized Drain Current (A)

Weakly Nonlinear Strongly Nonlinear Strongly Nonlinear Class A Class B/C

𝑾𝑯 𝒖 = 𝑾𝑬𝑫 + 𝒘𝒔𝒈𝒅𝒑𝒕 𝟑𝝆𝒈𝑵𝒖 + 𝜾𝑵 𝑾𝑯 𝒖 = 𝑾𝑬𝑫 + 𝒘𝒔𝒈𝒅𝒑𝒕 𝟑𝝆𝒈𝟐𝒖 + 𝒘𝒔𝒈𝒅𝒑𝒕 𝟑𝝆𝒈𝟑𝒖 + 𝜾 𝑱𝑬 𝒖 = 𝟒𝑾𝑯

𝟑 𝒖 − 𝟑𝑾𝑯 𝟒 𝒖

2 4 6 8 10 30 40 50 60 Class A DE (%) 2 4 6 8 10 60 70 80 90 Class B DE (%) 2 4 6 8 10 70 75 80 85 90 Frequency Radio f 2/f1 Class C DE (%)

Parallel, single-band Single, multi-band Parallel, single-band Parallel, single-band Single, multi-band Single, multi-band

Efficiency Comparison

 Compressed drain efficiency for

parallel single-band power amplifier

 Class-A: 𝜃𝑏𝑤𝑓 = 56%  Class-B: 𝜃𝑏𝑤𝑓 = 80%  Class-C: 𝜃𝑏𝑤𝑓 = 84%

 Compressed drain efficiency for

single multi-band power amplifier

 Class-A: 𝜃𝑏𝑤𝑓 = 31%  Class-B: 𝜃𝑏𝑤𝑓 = 67%  Class-C: 𝜃𝑏𝑤𝑓 = 75%

 Outputs are ideally filtered to remove

all non-linear distortion at the LOAD

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Efficiency Comparison

 There is a significant drop in

efficiency in the single, multi-band architecture

 Class-A: Reduction of 25%  Class-B: Reduction of 13%  Class-C: Reduction of 9 %

 This is due to the reduced power

in each band

 This is improved by overdriving the

amplifier

 Variation in efficiency as a

function of frequency ratio can be predicted by the peak-to-average- ratio of the input

 Lower PAR leads to higher drain

efficiency

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1 2 3 4 5 0.5 1 Drain Current (A) 1 2 3 4 5 0.5 1 Drain Current (A) Time (sec)

Freq. DC fL fH 0.25 0.25 0.5 Freq. DC fL fH 0.5 0.5 0.5

Single, multi-band Parallel, single-band

Linearity Comparison

 Linearity is especially critical in concurrent multi-band

systems

 Parallel, single-band architecture

 Nonlinear distortion causes harmonic generation only  Linearity of diplexer may be an issue  No limitations on frequency separation

 Single, multi-band architecture

 Nonlinear distortion causes harmonic AND intermodulation components  Restrictions on frequency choices

 Becomes much more complicated for larger number of bands

 Both cases will require good filtering at the output

 Filtering in the parallel, single-band case will depend on the diplexer

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Area Comparison

 Component count can be a good indication of board area

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Component Count Input L-Match 2M Output L-Match 2M RF Chock 2M RF Bypass 2M Power Transistor M Power Combiner 1 Total 9M+1

*M is the number of supported bands

IMN OMN

M1

IMN OMN

M2

IMN OMN

MM

+

P01 + P02 + … + P0M VDD VB

Component Count for Parallel Single-band Architecture

Area Comparison

 To now we have assumed ideal summation of the

• utput signals

 Practical implementations will use diplexer

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Ref. Insertion Loss Area TDK 202690DT ~0.4 dB 2 × 1.3 mm2 TDK 105950DT ~0.5 dB 1 × 0.5 mm2 Zou et al., MWCL 2012 ~0.5 dB 14 × 8.2 mm2 Dai et al., ICMMT 2012 ~0.5 dB 3 × 4 mm2 Chongcheawchamnan et al., MWCL 2006 ~3.4 dB 55 × 31 mm2 Hayati et al., TMTT 2013 ~3.5 dB 90 × 90 mm2

IMN OMN

M1

IMN OMN

M2

IMN OMN

MM

+

VDD VB

Practical summation block cannot be ignored 3-bands 2-bands

Area Comparison

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Component Count Input L-Match 2M Output L-Match 2M RF Chock 2 RF Bypass 2 Power Transistor 1 Power Combiner N/A Total 4M+5

*M is the number of supported bands

Component Count for Single, Multi- band Architecture

IMN OMN

M1 VB

Area Comparison

 Area is further compared using an example implementation

 Assume a lumped-element implementation of both architectures  Assume dual-band support  20% added to account for routing

08/05/15 15 Component Area/ (Technology) Parallel Single-Band Single Multi-Band

• Num. of

Components Area

• Num. of

Components Area Inductor/Capacitor (Matching Network) 0.125 mm2/ (0201) 8 1 mm2 8 1 mm2 RF Choke Inductor 0.5 mm2/(0402) 4 2 mm2 2 1 mm2 RF Bypass Capacitor 31 mm2/(2917) 4 124 mm2 2 62 mm2 Power Transistor 36 mm2/ Cree GaN FET 2 72 mm2 1 36 mm2 Diplexer 40 mm2/Ave. 2- band diplexers 1 40 mm2 Total 19 286 mm2 13 120 mm2

Conclusions

 Two popular power amplifier architectures for supporting concurrent

multi-band signaling have been compared

 Efficiency

 Parallel, single-band architecture

 Much higher efficiency for class-A  Gap is reduced for class-B and –C  Additional reduction in efficiency due to diplexer

 Single, multi-band architecture

 Reduced output power, per band, for the same DC bias  Efficiency depends upon frequency ratio as well as initial phase offset

 Linearity

 Parallel, single-band architecture

 Essentially the same linearity requirements as traditional single-band amplifiers

 Single, multi-band architecture

 Significant harmonic and inter-modulation distortion  Limits the choice of frequency bands  Becomes more severe as the number of supported bands increases

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Conclusions

 Area

 Parallel, single-band architecture

 Requires significantly more components  Diplexer

 Single, multi-band architecture

 Requires only a single set of RF choke and RF bypass devices

 The need for a diplexer will be the limiting factor for the

parallel, single-band architecture

 Large – Ranging from 0.5 to 115 mm2 for dual band and

12 to 8100 mm2 for triple band

 Lossy – Triple-band diplexers have insertion losses of several dB  Expensive – Commercial examples cost in the dollar range  Unclear how more than three bands can be supported

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Acknowledgements

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Zhen Zhang and Yifei Li

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Thank You

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