and Wafer-Scale Assembly Technologies May 17, 2010 CS MANTECH - - PowerPoint PPT Presentation

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and Wafer-Scale Assembly Technologies May 17, 2010 CS MANTECH - - PowerPoint PPT Presentation

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Wafer-Level Packaging and Wafer-Scale Assembly Technologies May 17, 2010 CS MANTECH Workshop 6 Portland OR Patty Chang-Chien Northrop Grumman Aerospace Systems Acknowledgement Multi-center effort at NGAS: Microelectronics, RF Product

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SLIDE 1

May 17, 2010 CS MANTECH Workshop 6 Portland OR

Patty Chang-Chien Northrop Grumman Aerospace Systems

Wafer-Level Packaging and Wafer-Scale Assembly Technologies

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SLIDE 2

Acknowledgement

  • Multi-center effort at NGAS: Microelectronics, RF Product Center,

Manufacturing, Product Engineering, Materials, Antenna Product

  • Kelly Hennig, Xiang Zeng, David Eaves, Phil Hon, Peter Chou, Gerry Mei,

Roger Tsai, David Farkas, John Chen, Keang Kho, Mike Battung, Yun Chung, Pei-Lan Hsu, Jeff Yang, Wendy Lee, Matt Nishimoto, Tony Long, Greg Rowan, Sean Shih, Dah-Weih Duan, Jose Padilla, Pin-Pin Huang, Minhdao Truong, Richard To, K.K. Loi, Hui Ma, Jeremy Ou-Yang, Craig Geiger, Gershon Akerling, Chi Cheung, Sujane Wang, Jane Lee, Danny Li, Peter Nam, Peter Ngo, Martin IIyama, Ging Wang, Tom Chung, Gary Gurling, Randy Duprey, Cesar Romo, Ben Heying, Randy Sandhu, Ben Poust, Matt Parlee, Denise Leung, David Eng, Eric Kaneshiro, Rich Kono, Jansen Uyeda, Mike Barsky, Jennifer Gan, Ke Luo, Fred Dai, Edna Yamada, Mike Wojtowicz, Rich Lai, Augusto Gutierrez, Aaron Oki and many more!

2

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SLIDE 3

Agenda

  • Overview

– Technology description – Benefits

  • 2-Layer WLP/WSA

– Process description – Examples

  • Interconnects & Transitions
  • Package Performance
  • Multi-Layer WLP/WSA

– Process description – Examples

  • Higher Order Integration

3

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SLIDE 4

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What is Wafer-Level-Packaging?

  • Add inter-cavity interconnects and cavity ring
  • Stack and bond multiple wafers, then dice
  • Forms a hermetically packaged 3-D integrated circuit
  • Enables integration of different MMIC technologies

3-D Wafer Scale Assembled IC State-of-the-art MMIC Wafer

Wafer-Level Packaging (WLP) AKA: Micro Packaging AKA: Wafer-Scale Assemlby (WSA)

WLP provides low cost, high volume, hermetic packaging

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SLIDE 5

5

Advanced Capabilities for Next-Generation Systems

  • WLP

performance superiority

– Advanced integration

  • best semiconductor technology for the function

– Ultra-compact, light weight packaging

  • size & weight savings

– High functional density & low loss interconnects

  • Superior circuit performance

– Hermetic MMIC packaging

  • Enhanced circuit reliability
  • WLP

Affordability

– Batch fabrication processes

  • Low cost, high volume

– Fully compatible with NGAS MMIC production processes

  • Existing & proven MMIC technologies
  • Next-generation MMIC technologies

– Reduce higher order assembly cost, relax module assembly requirement Large Aperture Phased Arrays Restricted Military Systems Satellite Comm.

  • Next-generation system needs performance superiority & affordability
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SLIDE 6

6

  • Superiority

– Hermetic compact MMIC packaging – Performance enabler

  • High functional density
  • Superior circuit performance
  • Affordability

– Batch fabrication processes, low cost, high volume – Reduce higher order assembly cost, relax module assembly requirement

WLP Benefits

Integrated Microwave Assembly (IMA) Wafer-Level- Package (WLP) Size reduction 1 1,000X Weight reduction 1 1,000X Cost reduction 1 10-100X

WLP offers superiority in performance and affordability in cost

Heterogeneous Integration using WLP

Combine multiple MMIC wafers by wafer bonding technology Tri-layer WLP TR Module X-band operation Mass: <15mg Size: 2.5mm x 2mm x 0.46mm WLP content: 3 bit PS, LNA, PA

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SLIDE 7

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GaAs InP GaN CMOS

Integrated Microwave Assembly Packaging

IMA

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SLIDE 8

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Wafer-Level Integration Benefits

  • Hermetic
  • Ultra-light weight, ultra-compact
  • Low cost, high volume
  • Performance enhancement

IMAs Wafer-Level Integrated Package

Weight: < 50 mg Size: mm x mm x mm Assembly: mass parallel, wafer scale Weight: g to >1000g Size: cm x cm x cm Assembly: serial, manual

Package near a thumb tack

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SLIDE 9

9

  • WLP is assembled using a low temperature wafer bonding process
  • WLP technology is fully compatible with NGAS MMIC production

processes

Low temperature wafer bonding process is key to MMIC compatible, robust WLP

Integration Using Wafer-Level Packaging

Circuit with Wafer Bonding Ring

–40 –30 –20 –10 Through Via Circuit (low-noise amplifier) Wafer Bonding Bonding Ring (wafer 1) Bonding Ring (wafer 2)

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SLIDE 10

2-LAYER WLP

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SLIDE 11

2-Layer WLP

BICIC ICIC Wafer 1 Wafer 2 Bonded pair Flip & align Wafer Bonding BICIC ICIC Wafer 1 Wafer 2 Bonded pair Bonded pair Flip & align Wafer Bonding

  • Wafers are individually processed prior to bonding

– No changes to standard MMIC processes

  • ICIC = Intra-Cavity InterConnections
  • BICIC = Backside ICIC

Bonding Layer BICIC (backside) ICIC (Front side) Bonding Layer BICIC (backside) ICIC (Front side)

2-layer Bonding Process Flow 2-layer Bonding Process Flow

2-Layer WLP is constructed by bonding 2 individually processed wafers

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SLIDE 12

12

WLP Demonstrations

Frequency bands w/ WLP

  • X-band

Ka-band

  • Ku-band

Q-band

  • V-band

W-band

  • WLP is fully compatible with NGAS’s MMIC production processes

NGAS has extensive experience in heterogeneous integration using WLP

Different compound-semiconductor technologies w/ WLP InP HEMTs InP HBTs ABCS HEMT GaAs HEMTs MEMS switches GaAs HBTs Passives GaAs Schottky diodes GaN HEMTs InP diodes Different circuit types w/ WLP

  • LNAs

PAs

  • Oscillators Phase shifters
  • Shift registers Switches

Substrate combinations w/ WLP

  • GaAs + GaAs
  • InP + GaAs
  • InP + InP
  • Quartz + Quartz
  • Si + InP
  • Glass + Glass
  • GaAs + Duroid
  • GaAs + InP + GaAs
  • GaAs + InP + InP
  • SiC + SiC
  • Multiple GaAs integrations
  • Multiple InP integrations
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SLIDE 13

Examples of Packaged MMICs

5 10 15 20 25 30 5 10 15 20 25 Frequency (GHz) S21 (dB)

Ku Band LNA, WLP GaAs HEMT circuit

5 10 15 20 25 30 5 10 15 20 25 Frequency (GHz) S21 (dB)

Ku Band LNA, WLP GaAs HEMT circuit

5 10 15 20 25 5 10 15 20 25 Frequency (GHz) S21 (dB)

Ku Band PA, WLP GaAs HEMT circuit

WLP Q-Band LNA (IRFFE)

  • 40
  • 30
  • 20
  • 10

10 20 10 20 30 40 50 Frequency (GHz) S21 (dB)

LNA Bonding Ring LNA Bonding Ring

Q-Band LNA, WLP GaAs HEMT Circuit

2 4 6 8 10 12 14 16 80 85 90 95 100 105 110 Frequency (GHz) S21 (dB)

W-Band PA, WLP GaAs HEMT circuit

2 4 6 8 10 12 14 16 80 85 90 95 100 105 110 Frequency (GHz) S21 (dB)

W-Band PA, WLP GaAs HEMT circuit

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SLIDE 14

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Wafer Level Packaging (WLP) MMICs Proven across the bands

KU KA Q

4-bit PHSH

  • Chip size: x=3.3mm, y=2.7mm
  • TTL compatible
  • avg RMS Amp Error=1.08dB
  • avg RMS Phase Error=16.5º

2-Stage, self-biased LNA

  • Chip size: x=3.3mm, y=2.7mm
  • bias: 4V, 26 mA
  • Gain > 26.5 dB at 16 GHz

2-Stage PA

  • Chip size: x=3.3mm, y=2.7mm
  • bias: 4V, 120 mA
  • Gain > 19 dB at 16 GHz

3-Stage, self-biased LNA

  • Chip size: x=4.2mm, y=4.2mm
  • bias: 4V, 45 mA
  • Gain > 24 dB at 35 GHz

3-Stage, self-biased LNA

  • Chip size: x=4.2mm, y=4.2mm
  • bias: 4V, 60 mA
  • Gain > 11.8 dB from 30-50 GHz

Miniaturized WLP T/R modules for large arrays

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SLIDE 15

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GaN WLP Technology

  • Developed world’s first GaN wafer level package process for record

power density

  • Demonstrated >99% GaN WLP interconnect yield

GaN WLP chip GaN WLP TEG chip Passive Cover Wafer Active GaN Wafer

Photo of GaN WLP MMIC

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SLIDE 16

W-Band WSA Oscillator

  • W-Band oscillator with built-in on chip

resonant cavity

  • 2-layer active MMIC integration:

– InP HEMT + GaAs HBT

Demonstrated 2-Layer WSA Oscillator

Photo of the integrated oscillator chip

1st and 2nd Half of Resonant Cavity Through Wafer RF Transition Active Device Coupling Slot Through Wafer RF Transition (Backside Probe Location) 1st and 2nd Half of Resonant Cavity Through Wafer RF Transition Active Device Coupling Slot Through Wafer RF Transition (Backside Probe Location)

Measured spectrum of Oscillator

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SLIDE 17

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Comparison of WLP and non-WLP circuits

ALH140 vs. ALH140V3

2 4 6 8 10 12 14 16 18 30 31 32 33 34 35 36 37 38 39 40 Frequency (GHz) S21 (dB)

ALH140_1 ALH140_2 ALH140_3 ALH140_4 ALH140_5 ALH140_6 ALH140_7 ALH140_8 ALH140_9 ALH140_10 ALH140_11 ALH140_12 ALH140_V3_1 ALH140_V3_2 ALH140_V3_3 ALH140_V3_4 ALH140_V3_5 ALH140_V3_6 ALH140_V3_7 ALH140_V3_8 ALH140_V3_9 ALH140_V3_10 ALH140_V3_11 ALH140_V3_12

: Conventional ALH140 (FIDR1/A-J103 1146A-031) : ALH140V3 with WLP cover (WLP5/1/P200-001) ALH 140 ALH 140V3 (WLP) 2.5mm 3.2mm 1.9mm 1.4mm

RF performance similar for WLP and non-WLP circuits

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SLIDE 18

2-LAYER INTEGRATED WLP/WSA EXAMPLES

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SLIDE 19

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Heterogeneous Integration Example

  • Integrated RF front end module with antenna

– Amplifier (GaAs HEMT) – 3 bit phase shifter (GaAs HEMT) – Interconnections (ICICs) – Antenna

WLP top side (antenna) WLP bottom side

Wafer Bonding Wafer 2 Wafer 1 Sealing Ring (Wafer 1) Sealing Ring (Wafer 2) Phase shifter Amplifier Ground Fence Through wafer via ICIC antenna Wafer Bonding Wafer 2 Wafer 1 Sealing Ring (Wafer 1) Sealing Ring (Wafer 2) Phase shifter Amplifier Ground Fence Through wafer via ICIC antenna

Integrated RF Front-End Module

Wafer 1

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SLIDE 20

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On-Wafer Measured Data

Amplifier S-Parameter Phase Shifter Phase States

  • WLP technology
  • Wafer1=passive, 4-mil GaAs
  • Wafer2=0.1um, 4-mil GaAs
  • 2-stage balanced Amplifier
  • 3-bit reflective phase shifter

100 200 300 400 1 2 3 4 5 6 7 8 Phase States Phase (deg)

  • 40
  • 20

20 10 20 30 40 50 Frequency (GHz) Magnitude (dB)

S21 S22 S11

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SLIDE 21

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WLP Linear Array Demonstration

Beam Forming Network (board) Integrated RF front-end modules w/ antenna

  • Demonstrated fully functional front-end

modules with a linear 4-element array

– GaAs HEMT + passive – Amplifier + 3bit PS + antenna in an integrated Q-Band WLP package – Successful integration to BFN board – Demonstrated electronic beam steering

  • 60
  • 40
  • 20

20 40 60

  • 40
  • 35
  • 30
  • 25
  • 20
  • 15
  • 10
  • 5

(deg) E-Field Magnitude (dB)

= 0 =15 Measured Beam Pattern

WLP top side (antenna) WLP bottom side

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SLIDE 22

INTERCONNECTS & TRANSITIONS

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SLIDE 23

RF ICICs

  • RF ICIC 50 Ohm Coaxial Transition
  • Designed to provide minimal mismatch between 50 Ohm microstrip line (wafer

1) and 50 Ohm CPW line (wafer 2)

Measured Data from RF ICIC Structure (2 RF ICIC transition + thru line)

  • 1
  • 0.9
  • 0.8
  • 0.7
  • 0.6
  • 0.5
  • 0.4
  • 0.3
  • 0.2
  • 0.1

5 10 15 20

Frequency (GHz) S21 (dB)

(a) (b)

Measured Data from RF ICIC Structure (2 RF ICIC transition + thru line)

  • 1
  • 0.9
  • 0.8
  • 0.7
  • 0.6
  • 0.5
  • 0.4
  • 0.3
  • 0.2
  • 0.1

5 10 15 20

Frequency (GHz) S21 (dB)

(a) (b)

Wafer 2 – ICIC Coaxial transition to CPW transmission line Wafer 1 – Microtransmission line to ICIC Coaxial transition

Demonstrated Low Loss, RF ICICs

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SLIDE 24

Low Loss RF Vias

  • RF via transitions

– Low loss up to 50GHz – <0.1dB insertion loss up to 30GHz

  • DC interconnects

– > 99% yield

  • Calibration structures

– To ensure accurate measurement

Measured Data Simulation

RF calibration and Test Structures RF Via Test Structure

Demonstrated Low Loss RF Vias for WLP devices

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SLIDE 25

High Frequency RF Interconnects

Bottom Wafer

Ground Vias connecting top and bottom ground planes

Bottom Wafer Top Wafer

Input Output

Back-to-Back Interconnect Cross Section

  • First-of-a-kind W-band WLP RF interconnect

— Insertion Loss < 0.2 dB — Return Loss > 20 dB — 20 dB isolation

Demonstrated Low Loss, High Isolation W-Band WLP Interconnects

Electro-Magnetic Simulation of Transition Measured Transition-Line-Transition Response ~0.2 mm

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SLIDE 26

Isolation Using Ground Fence

  • Isolation fence can be built using 3D

interconnects within WSA

  • Demonstrated 30dB isolation improvement

in W-band using ground fence

  • 3D WSA offers design flexibility and

performance improvement

RF Isolation Design For WSA MMIC

Simulated Isolation Fence Response

60 50 40 30 20 10

Blue: no via fence Red: with via fence

  • 60

Isolation Loss (dB) 91 97 Frequency (GHz)

Simulated Isolation Fence Response

60 50 40 30 20 10

Blue: no via fence Red: with via fence

  • 60

Isolation Loss (dB) 91 97 Frequency (GHz)

Measured Isolation Fence Response

No via fence Single via fence

  • 80

Isolation Loss (dB) 91 97 Frequency (GHz)

  • 60
  • 40
  • 20

Isolation Fence ICIC Thru-Wafer Via RF Transition Line

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SLIDE 27

PACKAGE PERFORMANCE

27

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SLIDE 28

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Package Mechanical and Thermal Integrity

  • WLP chips Passed the many military standard tests:

– Vibration-Sine

  • MIL-STD 883F, Method 2007.3, condition B

– Mechanical Shock (Pyroshock)

  • MIL-STD 883F, Method 2002.4, condition B

– Die Shear

  • MIL-STD 883F, method 2019.7

– Temperature Cycling

  • MIL-STD 883F, Method 1010.8, condition B
  • 55ºC to 125ºC, 50 cycles, MEMS
  • 55ºC to 85ºC, 300+ cycles, W-Band GaAs circuits
  • 55ºC to 125ºC, 500 cycles, GaAs PA

– Hermeticity

  • MIL-STD 883F, Method 1014.11
  • He fine leak, condition A2, flexible
  • Radioisotope fine leak, condition B
  • Penetrate dye gross leak, condition D
  • Environmental test: 85C 85% humidity 7 days Ku band GaAs MMICs

WLP packages are hermetic, thermally and mechanically robust

Mechanical Robustness Thermal Robustness Seal Robustness

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SLIDE 29

Thermal Robustness

  • 24 to 40 GHz GaAs HEMT LNA
  • Thermal cycling, -55 C to 125 C
  • 500+ cycles

29

  • 30
  • 25
  • 20
  • 15
  • 10
  • 5

5 10 15 20 1 11 21 31 41 S21 (dB) Frequency (GHz)

Post_500 Cycles Post_300 Cycles Post_100 Cycles Post_10 Cycles Pre_Cycle

Photo of WLP GaAs LNA Measured s21 response as function of thermal cycles

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SLIDE 30

MULTI-LAYER WLP/WSA

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SLIDE 31

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Advanced Integration: Multiple Layer WLP

Bonded Pair 1 Bonded Pair 2

Bonding Layer BICIC (backside) ICIC (Front side) Bonding Layer BICIC (backside) ICIC (Front side)

4-layer Bonding Process Flow

  • Example: 4-layer construction

– Use bonded pair as starting units

Process Bonding layer if necessary (backside) Wafer Bonding Bonded Pair 1 Bonded Pair 2

  • r single wafer

Multiple Layer WSA Flow

Process Bonding layer if necessary (backside) Wafer Bonding Bonded Pair 1 Bonded Pair 2

  • r single wafer

Multiple Layer WSA Flow

4-Layer Construction is Achieved By Bonding 2 bonded WLP pairs

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X-Band Tri-Layer Tx/Rx Modules

GaAs HEMT InP HBT Phase Shifter Switch Switch Shift Register Power Amplifier ABCS HEMT Low Noise Amplifier

WLP Tx/Rx Module

ABCS HEMT LNA InP HBT PA & digital control GaAs HEMT PS & Switches

Average mass: 12.9mg Size: 2.5mm x 2mm x 0.46mm

  • Next-Generation Large Aperture

Array T/R Module –Ultra light weight (<15 mg) –Extremely compact (<5 mm2 )

  • Transceiver Module Performance

–FOM > 10,000 –Reliability: MTTF >106 Hours

Demonstrated X-Band Integrated T/R Module

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SLIDE 33

Tri-Layer T/R Demo

  • Tri-layer T/R module demonstration

– GaAs HEMT + InP HBT + InP HEMT – Demonstrated excellent yield and T/R circuit performance

Measured NF (Rx) of the tri-layer WLP T/R module

33

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SLIDE 34

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8-bit CMOS Shift Register WLP 8-bit VAP 8-bit shift register WLP 8-bit VAP 5-mil solder ball

45 90 135 180 225 45 90 135 180

Set Angle (Deg) Measured Angle (Deg)

CLK ENB Data

Ideal Measured

Input Digital CTRL Waveform Measured Phase Shifter Data

CMOS + III-V V Integ egrat ration ion Demo

Demonstrated heterogeneously integrated CMOS flip-chip to WLP MMICs

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SLIDE 35

HIGHER ORDER ASSEMBLY

35

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SLIDE 36

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Assembly

  • Technologies integrated

– GaAs-GaAs – GaAs-InP – InP-InP – ABCS-InP-GaAs

  • Techniques demonstrated

– Epoxy to Fixture/Board – Bump to Board

  • Manual
  • Auto assembly

Demonstrations

  • CMOS to III/V Integration
  • Direct WLP to Board Attach
  • 16-element Ku-band Rx Array
  • 8-element Ku-band Rx Sub-

Array

  • 4-element Q-band Tx Array

WLP Higher Order Integration Demonstrations

Alumina Organic Board Fixture Benefit

 SWaP reduction  SWaP, cost reduction  Near term insertion  Design to manufacturing  mmW array implementation

Demonstrated WLP-to-Board Integration

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SLIDE 37

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Microbump: Chip-Board Integration

  • Developed microbump technologies for WLP–

to-board attachment and integration

Sn/Pb microbump array Cu stud microbump Microbumps on backside of the package

Microbumps enable direct WLP-to-Board Integration

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SLIDE 38

38

Direct Board Attach Using Microbumps

X-ray result showing good board to chip interface board chip Cu studs

Excellent Chip-to-Board Microbump Interface

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SLIDE 39

Example of Epoxy Attach and Ribbon Bonds Implementation

Integrated Subarray Antenna Board Ku Band subarray board with WLP chips

Azimuth ( ) Normalized Amplitude

0.0 25.0 45.0

  • 25.0
  • 45.0

Measured Far Field Pattern

Azimuth ( ) Normalized Amplitude

0.0 25.0 45.0

  • 25.0
  • 45.0

Measured Far Field Pattern

5 WLP MMIC fixture for environmental testing

WLPs are compatible with epoxy attachment

39

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SLIDE 40

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WLP on Interposer Boards on PWB

Front Side: WLP on Interposer Back Side (Solder Ball) WLP on Interposer WLP Interposer board attachment to PWB

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SLIDE 41

Higher Order Integration Using WLP/WSA

  • Demonstrated thermal cycling

robustness of WLP-board assembly with underfill

  • >200 cycles
  • from -40C to 100C
  • Pass without failure

Chips on the front side of PWB after backside assembly Chips on the backside of PWB Dual sided board WLP chips WLP chips

Dual-Sided Assembly

5mil Solder Balls

  • Successfully demonstrated dual

side WLP chip-to-board attachment

PWB 5mil solder balls 2-layer WLP chip underfill WLP cavity

41

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SLIDE 42

42

Summary

  • WLP technology offers performance superiority and affordability for

next-generation systems

  • WLP offers significant size, weight and cost savings for future

systems

  • Demonstrated multiple advanced technology integration with WLP
  • Verified robustness of WLP packaging by MIL-STD tests
  • Demonstrated WLP integrated MMICs & modules across the bands
  • NGAS is committed to mature and improve wafer-scale integration

technology for system insertion

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SLIDE 43

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