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Characterizing Wafer Delays in Cluster Tools for K-Cyclic Schedule KAIST Dong-Hyun Roh and Tae-Eog Lee 2015.10.16 ISMI 2015 Table of Contents 1. Introduction 2. Preliminaries 3. Wafer Delays in Cluster Tools 4. Wafer Delay Regulation

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SLIDE 1

KAIST Dong-Hyun Roh and Tae-Eog Lee 2015.10.16

ISMI 2015

Characterizing Wafer Delays in Cluster Tools for K-Cyclic Schedule

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SLIDE 2

Table of Contents

2015.10.16 ISMI

  • 1. Introduction
  • 2. Preliminaries
  • 3. Wafer Delays in Cluster Tools
  • 4. Wafer Delay Regulation Strategies
  • 5. Conclusion
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3/22

Introduction

  • Cluster tools are widely used semiconductor manufacturing tools. It usually

repeats a lot of tasks cyclically. If K timing patterns appear during a work cycle of a schedule, then the schedule is called a K-cyclic schedule. Usually, the tool has a K- cyclic schedule.

  • Some chambers in a cluster tool have wafer residency time, or wafer delay
  • constraints. If the residency time is longer than the constraints, then the wafers

cannot be used in real industries.

  • In a K-cyclic schedule, it is hard to recognize the wafer delays of PMs because of

the complexity of the schedule. Therefore it usually cannot assure the feasibility of the schedule for tight constraints.

  • In this research, we give explicit formulas for wafer delays in cluster tools. We

consider two types of cluster tools: single-armed cluster tools and dual-armed cluster

  • tools. And we introduce two wafer delay regulation methods, which are a workload

balancing and a feedback control.

Introduction

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Introduction

  • There have been numerous works on wafer delays in cluster tools.
  • 1. Schedulability analysis against an upper limit on wafer delays which is waiting

times within processing chambers [1], [3], [5], [6], [7], [8], [9]

  • 2. Stabilization and regulation of wafer delays [2], [6], [9], [10], [12], [13], [15], [17]
  • 3. Modelled and analyzed by TEGs and max-plus algebra [2], [4], [11], [14], [17], [18]
  • However, most works consider 1-cyclic schedules.
  • There were less works for identifying wafer delays itself.
  • Although Baccelli et al. [16] provides a recursion for token sojourn times at places,

we yet need a more direct insight on wafer delays.

Introduction

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Cluster Tools

  • Cluster tools are widely used semiconductor manufacturing tools.
  • It consists of several process modules(PMs), a wafer handling robot at the center
  • f the tool, and loadlocks.
  • The only one robot operation can perform at a time.
  • We assume that the robot operation times are identical.

Token Delays in Timed Event Graphs Preliminaries

PM1 PM2 PM3 PM4 Loadlock Loadlock

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Petri-nets and Event Graphs

  • Petri-net : a modelling framework for discrete event systems which consists of arcs,

tokens, places, and transitions.

  • Event graph : a kind of Petri-nets which every place has exactly a single input and
  • utput transition. Since it has no choice problem, the graph is called a decision-free

graph.

  • Timed event graph(TEG) : a kind of event graphs whose places have required token

holding times.

  • The behavior of a cluster tool can be regarded as a discrete event system, so it can be

modelled by a Petri-net. If the robot task sequence is fixed, the behavior can be modelled by a TEG.

Token Delays in Timed Event Graphs Preliminaries

Petri-net Event Graph

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6 π‘ˆ7 π‘ˆ8 π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6 π‘ˆ7 π‘ˆ8

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Timed Event Graphs

Token Delays in Timed Event Graphs Preliminaries

  • Circuit ratio : 𝑑𝑗𝑠𝑑𝑣𝑗𝑒 π‘ˆπ‘π‘™π‘“π‘œ πΌπ‘π‘šπ‘’π‘—π‘œπ‘• π‘ˆπ‘—π‘›π‘“π‘‘ Γ· 𝑑𝑗𝑠𝑑𝑣𝑗𝑒 # 𝑝𝑔 π‘ˆπ‘π‘™π‘“π‘œπ‘‘
  • Critical circuit ratio : 𝑛𝑏𝑦𝑑𝑗𝑠𝑑𝑣𝑗𝑒𝑑 𝐷𝑗𝑠𝑑𝑣𝑗𝑒 𝑠𝑏𝑒𝑗𝑝
  • Critical circuit : the circuit which has the critical circuit ratio.
  • Example)

2 2 2 2 2 2 2

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6 π‘ˆ7 π‘ˆ8

28 98 38 2

28 50 40 16

  • In cluster tools, the critical circuit means the work cycle of the bottleneck PM and

the critical circuit ratio means the average cycle time(𝝁) of the tool.

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K-cyclic Schedule

  • In this research, the schedule of a cluster tool means the firing epochs of transitions
  • f the TEG representing the behavior of the tool.

Definition) K-cyclic schedule Let 𝑦𝑗

𝑠 denote a 𝑠-th firing epoch of transition 𝑗. If 𝑦𝑗 𝑠+𝐿 βˆ’ 𝑦𝑗 𝑠 = π‘’πœ‡ is a constant but

𝑦𝑗

𝑠+𝑙 βˆ’ 𝑦𝑗 𝑠 is not βˆ€π‘™, 1 ≀ 𝑙 ≀ 𝐿, this schedule 𝑦𝑗 𝑠 βˆ€π‘—, 𝑠} is named a K-cyclic schedule.

And 𝐿 is called the cyclicity.

  • In a cluster tool, the cyclicity K is the # of parallel chambers of the bottleneck
  • process. And in a K-cyclic schedule, each PM has K values of wafer delays.

Definition) Time difference of a K-cyclic schedule πœ€ ∈ 𝑆+

𝐿 whose πœ€π‘— ≔ π‘¦π‘˜ 𝑗+1 βˆ’ π‘¦π‘˜ 𝑗 where transition π‘˜ is one of transitions in the critical

circuit is called the time difference of a K-cyclic schedule.

  • Since the critical circuit has no delay, the firing epochs of the critical circuit or the

bottleneck process determines the K-cyclic schedule. The wafer delays in PMs also dependent on the time difference.

  • Since it is K-cyclic schedule, 𝒋=𝟐

𝑳

πœΊπ’‹ = 𝑳 βˆ— 𝝁 where πœ‡ is the average cycle time of the tool.

Token Delays in Timed Event Graphs Preliminaries

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Time Difference

2 2 2 2 2 2 2

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ5 π‘ˆ6 π‘ˆ7 π‘ˆ8

28 148 38 2

28 50 40 16

1st-cycle 2nd-cycle 3rd-cycle

𝐿 = 3

𝑦4

1

𝑦4

2

𝑦4

3

πœ€1 ≔ 𝑦4

2 βˆ’ 𝑦4 1

πœ€2 ≔ 𝑦4

3 βˆ’ 𝑦4 2

πœ€3 ≔ 𝑦4

4 βˆ’ 𝑦4 3 𝑗=1 𝐿

πœ€π‘— = 𝐿 βˆ— πœ‡ = 150

Token Delays in Timed Event Graphs Preliminaries

π‘ˆ

4

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10/22

Single-armed and Dual-armed Cluster Tools

  • The cluster tools are classified according to the number of robot arms. And each tool

has its own optimal robot sequence for a serial-parallel wafer flow pattern.

  • Single-armed cluster tool : Backward sequence
  • Dual-armed cluster tool : Swap sequence
  • In this research, we consider two robot sequences and suppose there are no parallel

chambers except the bottleneck process.

Token Delays in Timed Event Graphs Wafer Delays in Cluster Tools

Backward Swap

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11/22

TEG for the Backward Sequence

  • The timed event graph for the backward sequence.
  • We define the workload of 𝑸𝑡𝒋 (𝑿𝑴𝒋) in the backward sequence : 𝒒𝒋 + πŸ‘π’— + πŸ‘π’Ž +

πŸ’π’˜ where π‘žπ‘— : the process time of 𝑄𝑁𝑗, 𝑣, π‘š, 𝑀 : a robot task time for unloading, loading, and moving/transporting, respectively.

  • The workload of a PM is the time needed of the PM to produce a wafer.
  • The workload of 𝑸𝑡𝒋 is the same as the circuit ratio of 𝑸𝑡𝒋 in a TEG.

𝑁13 𝑁𝑀2 𝑉3 𝑁3𝑀 𝑀𝑀 𝑉2 𝑁23 𝑀3 𝑉1 𝑁12 𝑀2 π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6 π‘ˆ7 π‘ˆ8 π‘ˆ9 π‘ˆ

10

π‘ˆ

11

π‘ˆ

12

𝑁2𝑀 𝑉𝑀 𝑁𝑀1 𝑀1 π‘ˆ

13

π‘ˆ

14

π‘ˆ

15

𝑁31 π‘ˆ

16

𝑄

1

𝑄

3

𝑄

2

Token Delays in Timed Event Graphs Wafer Delays in Cluster Tools

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12/22

Wafer Delays in Single-armed Cluster Tools

Token Delays in Timed Event Graphs Wafer Delays in Cluster Tools

Theorem 1) For a single-armed cluster tool with a single bottleneck π‘„π‘π‘—βˆ— and a cyclicity 𝑳, suppose the tool follows the backward sequence. Then the followings are satisfied:

  • 1. With satisfying 𝑙 πœ€π‘™ = 𝐿 βˆ— πœ‡, time differences πœΊπ’ ∈ [𝑿𝑴𝒋, 𝑳 βˆ— 𝝁 βˆ’

𝑳 βˆ’ 𝟐 βˆ— 𝑿𝑴𝒋] where 𝑿𝑴𝒋 is the maximum workload of 𝑸𝑡𝒋 (𝒋 β‰  π’‹βˆ—).

  • 2. For the bottleneck PM π‘—βˆ—, π’†π‘Έπ‘΅π’‹βˆ— = 𝟏.
  • 3. For downstream PMs (𝒋 > π’‹βˆ—), 𝒆𝑸𝑡𝒋 = 𝟏.
  • 4. For upstream PMs (𝒋 < π’‹βˆ—), 𝒆𝑸𝑡𝒋 = πœΊπ’ βˆ’ 𝑿𝑴𝒍, βˆ€π‘™ = 1, … , 𝐿.
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13/22

TEG for Swap Sequence

  • The timed event graph for the swap sequence.
  • We define the workload of 𝑸𝑡𝒋 (𝑿𝑴𝒋) in the swap sequence : 𝒒𝒋 + 𝒗 + π’Ž + 𝒔 where

π‘žπ‘— : the process time of 𝑄𝑁𝑗, 𝑣, π‘š, 𝑑 : a robot task time for unloading, loading, and swap, respectively.

  • The workload of 𝑸𝑡𝒋 is the same as the circuit ratio of 𝑸𝑡𝒋 in a TEG.
  • Since π‘‹π‘€π‘—βˆ—

𝑇π‘₯π‘π‘ž < π‘‹π‘€π‘—βˆ— 𝐢𝑏𝑑𝑙π‘₯𝑏𝑠𝑒 generally, a dual-armed cluster tool has more

productivity than a single-armed cluster tool.

𝑁𝑀𝑀 𝑄

1

𝑄

2

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6 π‘ˆ7 π‘ˆ8 π‘ˆ9 π‘ˆ

10

π‘ˆ

11

π‘ˆ

12

π‘ˆ

13

π‘ˆ

14

π‘ˆ

15

π‘ˆ

16

𝑄

3

𝑇1 𝑉𝑀 𝑁𝑀1 𝑉1 𝑀1 𝑁12 𝑉2 𝑀2 𝑁23 𝑉3 𝑇3 𝑀3 𝑁3𝑀 𝑀𝑀 𝑇2 Token Delays in Timed Event Graphs Wafer Delays in Cluster Tools

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Wafer Delays in Dual-armed Cluster Tools

Token Delays in Timed Event Graphs Wafer Delays in Cluster Tools

Theorem 2) For a dual-armed cluster tool with a single bottleneck π‘„π‘π‘—βˆ— and a cyclicity 𝑳, suppose the tool follows the swap sequence. Then the followings are satisfied:

  • 1. With satisfying 𝑙 πœ€π‘™ = 𝐿 βˆ— πœ‡, time differences πœ€π‘™ ∈ [𝑿𝑴𝑺, 𝑳 βˆ— 𝝁 βˆ’
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Wafer Delays in a Single-armed Cluster Tool (Example)

  • 3 PM, 𝐿 = 2, 𝑄𝑁2 is bottleneck : Backward Sequence

1) π‘ΈπŸ > π‘ΈπŸ’ β‡’ 𝜺𝟐 ∈ π‘Ώπ‘΄πŸ, πŸ‘π βˆ’ π‘Ώπ‘΄πŸ (πœ€2 = 2πœ‡ βˆ’ πœ€1) 𝑒𝑄𝑁1 = πœ€ βˆ’ 𝑋𝑀1, 2πœ‡ βˆ’ 𝑋𝑀1 βˆ’ πœ€ and 𝑒𝑄𝑁3 = 0, 0

Wafer Delays in Cluster Tools

πœ€1

𝑋𝑀1 2πœ‡ βˆ’ 𝑋𝑀1 𝑋𝑀2 = πœ‡

2(πœ‡ βˆ’ 𝑋𝑀1)

𝑄𝑁3 𝑄𝑁1

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16/22

Wafer Delays in a Single-armed Cluster Tool (Example)

  • 3 PM, 𝐿 = 2, 𝑄𝑁2 is bottleneck : Backward Sequence

2) π‘ΈπŸ ≀ π‘ΈπŸ’ β‡’ 𝜺𝟐 ∈ π‘Ώπ‘΄πŸ’, πŸ‘π βˆ’ π‘Ώπ‘΄πŸ’ (πœ€2 = 2πœ‡ βˆ’ πœ€1) 𝑒𝑄𝑁1 = πœ€ βˆ’ 𝑋𝑀1, 2πœ‡ βˆ’ 𝑋𝑀1 βˆ’ πœ€ and 𝑒𝑄𝑁3 = 0, 0

Wafer Delays in Cluster Tools

πœ€

𝑋𝑀3 2πœ‡ βˆ’ 𝑋𝑀3 𝑋𝑀2

2πœ‡ βˆ’ 𝑋𝑀1 βˆ’ 𝑋𝑀3

𝑄𝑁3 𝑄𝑁1

𝑋𝑀3 βˆ’ 𝑋𝑀1

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SLIDE 17

2πœ‡ βˆ’ 𝑋𝑀3 𝑋𝑀3

17/22

Wafer Delays in a Dual-armed Cluster Tool (Example)

  • 3 PM, 𝐿 = 2, 𝑄𝑁2 is bottleneck : Swap Sequence

1) π‘ΈπŸ > π‘ΈπŸ’ β‡’ 𝜺𝟐 ∈ [𝑿𝑴𝑺, πŸ‘π βˆ’ 𝑿𝑴𝑺] and suppose that 𝑋𝑀𝑆 β‰ͺ 𝑋𝑀1, 𝑋𝑀3. Note : The range between 𝑿𝑴𝑺~π‘Ώπ‘΄πŸ’, π‘Ώπ‘΄πŸ is relatively large.

Wafer Delays in Cluster Tools 𝑋𝑀1 2πœ‡ βˆ’ 𝑋𝑀1 𝑋𝑀2

2(πœ‡ βˆ’ 𝑋𝑀1)

𝑄𝑁3 𝑄𝑁1

2πœ‡ βˆ’ 𝑋𝑀𝑆 𝑋𝑀𝑆

2(πœ‡ βˆ’ 𝑋𝑀3) πœ€1

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18/22

Wafer Delays in a Dual-armed Cluster Tool (Example)

  • 3 PM, 𝐿 = 2, 𝑄𝑁2 is bottleneck : Swap Sequence

2) π‘ΈπŸ ≀ π‘ΈπŸ’ β‡’ 𝜺 ∈ [𝑿𝑴𝑺, πŸ‘π βˆ’ 𝑿𝑴𝑺] and suppose that 𝑋𝑀𝑆 β‰ͺ 𝑋𝑀1, 𝑋𝑀3. Note : The range between 𝑿𝑴𝑺~π‘Ώπ‘΄πŸ’, π‘Ώπ‘΄πŸ is relatively large.

Wafer Delays in Cluster Tools

πœ€1 2(πœ‡ βˆ’ 𝑋𝑀3)

2πœ‡ βˆ’ 𝑋𝑀1 𝑋𝑀1 𝑋𝑀3 2πœ‡ βˆ’ 𝑋𝑀3 𝑋𝑀2 2πœ‡ βˆ’ 𝑋𝑀𝑆 𝑋𝑀𝑆

𝑄𝑁3 𝑄𝑁1

2(πœ‡ βˆ’ 𝑋𝑀1)

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19/22

Wafer Delays Regulation Strategies

Wafer Delay Regulation Strategies

  • We introduce two approaches to control wafer delays : feedback control and

workload balancing.

1 1 𝑒3 𝑒2 𝑒4 2 3 5 𝑒1 delay => 0 𝑒𝑣 2 5

Feedback Control

2 2 2 2 2 2

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6

28 98 2 2 2 2 2 2

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6

28 98 20 18

Workload Balancing

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20/22

Feedback Control

  • Kim et al. [12][13] studied a specialized feedback control for cluster tools. By using

their methodology, wafer delays of a certain PM can be controlled not to exceed the predetermined threshold regardless of the cyclicity.

  • We use feedback control in a different way: control time difference 𝜺.

For example, suppose that we want to equalize wafer delays of PMs. Since delays are πœ€π‘™ βˆ’ 𝑋𝑀𝑗, the equal values of wafer delays can be obtained by equalizing πœ€π‘™ as πœ‡, for all 𝑙 ∡ π‘˜=1

𝐿

πœ€

π‘˜ = 𝐿 βˆ— πœ‡ . β‡’ 𝒆𝑸𝑡𝒋 𝒍

= 𝝁 βˆ’ 𝑿𝑴𝒋

  • Idea : Add an arc with a single token which has the critical circuit ratio.
  • Since K is π‘š. 𝑑. 𝑛. {𝑕. 𝑑. 𝑒. # 𝑝𝑔 π‘’π‘π‘™π‘“π‘œπ‘‘ 𝑝𝑔 π‘π‘’π‘˜π‘π‘‘π‘“π‘œπ‘’ π‘‘π‘ π‘—π‘’π‘—π‘‘π‘π‘š 𝑑𝑗𝑠𝑑𝑣𝑗𝑒𝑑 }, 𝑳 = 𝟐.

Token Delays in Timed Event Graphs Wafer Delay Regulation Strategies 𝑁𝑀𝑀 𝑄

1

𝑄

2

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6 π‘ˆ7 π‘ˆ

10

π‘ˆ

11

π‘ˆ

12

π‘ˆ

13

π‘ˆ

14

π‘ˆ

15

π‘ˆ

16

𝑄

3

𝑇1 𝑉𝑀 𝑁𝑀1 𝑉1 𝑀1 𝑁12 𝑉2 𝑀2 𝑁23 𝑉3 𝑇3 𝑀3 𝑁3𝑀 𝑀𝑀 𝑇2 π‘ˆ9 π‘ˆ8

𝑳 = 𝟐

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21/22

Workload Balancing

  • Lee et al. [18] studied about the workload balancing strategies for cluster tools.
  • The key idea is to reduce the imbalance of circuit ratios by postponing robot tasks

appropriately, i.e., increasing token holding times of robot task places in the TEG. Case 1) Case 2)

Token Delays in Timed Event Graphs Wafer Delay Regulation Strategies 2 2 2 2 2 2

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6

28 98 20 2 2 2 2 2 2

π‘ˆ

1

π‘ˆ2 π‘ˆ3 π‘ˆ

4

π‘ˆ5 π‘ˆ6

28 98 38

Since there are no delays in the critical circuits, π‘Έπ‘΅πŸ has no delays.

𝑄

1

𝑄

2

𝑄

1

𝑄

2

Again 𝑳 becomes 1, so wafer delays of π‘Έπ‘΅πŸ are equalized.

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22/22

Conclusion

  • We have characterized the wafer delays in cluster tools for a given K-cyclic

schedules.

  • The closed form formulas describe how the delays occur. Also, it is known that the

backward sequence is better than the swap in respect of wafer delays.

  • We also have suggested two wafer delay regulation methods: feedback control and

workload balancing.

  • Our further works include to generalize this study for general series-parallel PMs.
  • Analyses for worst-case delay are also included.
  • We may improve wafer delay regulation methods with different and practical

constraints.

Token Delays in Timed Event Graphs Conclusion

slide-23
SLIDE 23

Question?

2015.10.16 ISMI

slide-24
SLIDE 24

Reference

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SLIDE 25

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