MS Final Exam Frequency Diversity Wideband Digital Receiver And Signal Processor For Solid-State Dual-Polarimetric Weather Radars Kumar Vijay Mishra Advisor: Dr V. Chandrasekar Committee: Dr A. Jayasumana and Dr P. Mielke Jr. June 15, 2012 Background Photograph by Kumar Vijay Mishra
MS Final Exam Outline • Introduction • Context of Solid-State Transmitters in Weather Radars • Existing Weather Radar Digital IF Receivers • Digital Receiver solution for Solid-State Transmitter Weather Radars • Multi-Channel Receiver Design • Processing Modes • NASA D3R System • First Results from Field Deployment • Summary 2/61
MS Final Exam Signal Theory of Weather Radars • Weather radar equation (Probert-Jones, 1962) • Δ r = c τ /2 Radar observables in terms of backscattering matrix Range R H-Transmitter To H-receiver h- port Duplexer STALO/ COHO Duplexer v- port V-Transmitter To V-receiver Tx - H Tx - V Rx - H S hv S hv S hh S hh Rx - V Sinclair Matrix 3/61 S vh S vv S vh S vv
MS Final Exam Context of Solid-state transmitters for weather radars • WWII: Weather echoes identified as clutter on military radars (Atlas et. al. , 1990) • 1950s: Application of backscatter matrix in radar (Kennaugh, Ohio State) • 1975 (Ulbrich et. al. ): Backscatter matrix application to meteorological radars • 1976 (Seliga and Bringi): Polarization diversity in weather radars • 1979 (Seliga et. al. ): First measurement of Z dr with CHILL • Early-to-mid 1990s (Klazura et. al. ): Ground-based scanning weather radar network (WSR-88D) • Mid-1990s (Ackerman and Stokes): ARM program for vertically-pointing radars • 1996: First weather radar digital IF receiver introduced by Vaisala • 1997 (Kummerow): First spaceborne weather radar (TRMM) • Early 2000s: X-band weather radar networks (CASA IP1) • Late 2000s: Solid-state transmitters for weather radars (HIWRAP, WiBEX, D3R) • Low operating power, high duty cycle, higher reliability, extremely wide bandwidth, digital control, longer operating life 4/61
MS Final Exam Aspects of solid-state transmitter weather radars • The intensity of the weather is determined by measuring the reflectivity of the volume of precipitation particles. • Reflectivity is measured from the received signal at the antenna reference port: [Bringi and Chandrasekar, 2002] • min(Z e ) is a function of transmit pulse width for a given transmitter and antenna. • Long transmit pulses (= degraded range resolution) are required for adequate sensitivity in low-power solid-state transmitters. 5/61
MS Final Exam Aspects of solid-state transmitter weather radars (contd.) • Pulse Compression waveforms can enable solid-state transmitter technology • Improves range resolution and reduces peak-power requirement • Increases sensitivity • Improves accuracy of estimates through range averaging • Increases dynamic range beyond RF hardware limitations • Common usage in hard target radars (Lewis et. al. , 1986) and lidars (Oliver, 1979) • Use in weather radars has been limited • Range sidelobes degrade measurements for volume targets • Introduces blind zones in the measurements • Implications of wider bandwidth (Yoshikawa, 2010) 6/61
MS Final Exam Aspects of solid-state transmitter weather radars (contd.) • Frequency diversity waveforms • Multiple subpulses transmitted to avoid blind zones (Bharadwaj et. al. , 2009) • Low ISL pulse compression filters employed • Multi-channel wideband digital receivers • Potential deployment of waveforms • D3R (Operational) (Chandrasekar et. al. , 2010) • WiBEX (Under development) (George et. al. , 2010) 7/61
MS Final Exam Existing Weather Radar Digital IF Receivers Context of a generic digital receiver in a radar system Commercial Solutions: Vaisala RVP Series (NEXRAD, TDWR), GAMIC ENIGMA series (DWD, Radtec), Gematronik GDRX series (Australian and Dutch weather radar network). Research Solutions: CSU-CHILL Digital Receiver (George, 2007), CASA EDAQ Series (Khasgiwale, 2005), USRP-II (Vierinen et. al. , 2009) Multi-pulse frequency diversity processing is currently not available on these receivers 8/61
MS Final Exam Common Features of Weather Radar Digital IF Receivers • Operational Requirements • Performance Requirements • Polarization agility • Wide dynamic range • Polarization diversity • Dual PRF and Staggered PRT processing • On-board transmit control • Multi-trip echo recovery • Calibration, Test and • Pulse compression Debugging • Clutter filtering • Transmit pulse sampling • Attenuation correction • BIST and BITE 9/61
MS Final Exam Outline • Introduction • Context of Solid-State Transmitters in Weather Radars • Existing Weather Radar Digital IF Receivers • Digital Receiver solution for Solid-State Transmitter Weather Radars • Multi-Channel Receiver Design • Processing Modes • NASA D3R System • First Results from Field Deployment • Summary 10/61
MS Final Exam Wideband Digital IF Receiver Hardware • Hardware PCI • Pentek 7150 board with Quad 200MHz PMC P4 Interface Interface 16-bit TI ADS5485 ADCs with Virtex - 5 SX95T as processing FPGA • Software • Pentek libraries (ReadyFlow) for PCI- based communication Standard FPGA development software • (ModelSim, ISE, ChipscopePro) • Function • Analog to digital conversion of IF signal Digital downconversion • 26-Pin LVPECL SMC Connectors Front Panel • Digital pulse compression for signal and clock inputs • Framing, antenna position decoding, IRIG-B decoding 11/61
MS Final Exam Digital Receiver Board 4733 PMC 7150 PMC • Development environment Adapter • PMC mounted on Technobox 4733 PMC adapter and 4936 Fan assembly • Field deployment • Single board computer and cPCI carrier board with a PMC slot (Concurrent Technologies) 4936 Fan Assembly PMC DRX card mounted on a single- board computer 7150 PMC mounted on the chassis of a lab computer 12/61
MS Final Exam Block Diagram of DRX Hardware 13/61
MS Final Exam DRX Hardware Features • Processing FPGA • The digitized data from ADCs is sampled and processed • Available for user to configure • Interface FPGA • Board interfaces (PCI-X, PCIe) • Not accessible to the user Onboard clock and timing circuits • • Four ADCs, DDR2 SDRAM • Voltage and temperature sensors • LVPECL, LVDS, SMC, Custom I/O interfaces available Separate connectors for external clock and • PPS signals Sample output for a successful sensor data query 14/61
MS Final Exam Principle of Operation and Interfaces • PMC Baseboard Interface • SBC communication and LVDS Connections • SMC inputs for RF signals, clock and PPS • FPGA interfaces • Online configuration through Interface FPGA • JTAG assembly interface for debugging • DMA Interrupts, temperature and voltage sensors Waveform generator (George et. al. , • 2010) • System triggers through SCSI • Modbus programming • Antenna position interface GPS timestamp interface • 15/61
MS Final Exam Outline • Introduction • Context of Solid-State Transmitters in Weather Radars • Existing Weather Radar Digital IF Receivers • Digital Receiver solution for Solid-State Transmitter Weather Radars • Multi-Channel Receiver Design • Processing Modes • NASA D3R System • First Results from Field Deployment • Summary 16/61
MS Final Exam Digital Receiver FPGA Design Requirements • Total number of channels = 12 (Two polarizations for three subpulses downconverted to I and Q) • Cost of filter chain for all twelve channels is expensive in terms of logic and multipliers • Other Requirements/Features • Process all range gates for each channel (including transmit pulse sample) • Programmable Built-In Self Test (BIST) option • Online digital health report • Option of data available without pulse compression • Several configurable features and scalability • Programmable sampling (1MHz to 10 MHz) • Multiple DMA data transfer logic • Simultaneously archive time-series for all 12 channels on RAID • Interface with Positioner and GPS decoder software 17/61
MS Final Exam Design Philosophy • Xilinx Virtex-5 SX95T FPGA • SXT family is rich in signal processing resources • 14720 Logic Slices, 640 DSP48Es, 6 CMTs, ~10 Mb RAM, f max = 550 MHz • IF Subsampling required (Narrowband interpretation of Nyquist criterion) Three-pulse waveform at IF=140MHz Inverted image of the signal at 60 MHz 18/61
MS Final Exam Design Philosophy (contd.) • Virtex SXT95 FPGA • Pentek ’ s own design occupies 50% of the logic • Design Challenge • Cost of filter chain: MATLAB Implementation of one subpulse channel Filter Taps Mults DSP48Es (MATLAB) (FPGA) Halfband Filter 1 23 13 4 Halfband Filter 2 23 13 4 Decimation Filter 255 205 13 21 Cascade of 301 231 Decimation Filters (= 1+2+3) 40 µs Pulse 400 401 22 Compression Filter 20 µs Pulse 200 201 12 Compression Filter Total 833 (130%) 55 (8%) SX95T has only 640 DSP48Es: resource savvy FPGA design is required. • 19/61
MS Final Exam D3R Multichannel Pulse Compression Digital Receiver 20/61 An illustration of the design
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