Analysis and Optimization of Analysis and Optimization of Thermal - - PowerPoint PPT Presentation

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Analysis and Optimization of Thermal Issues in High Performance VLSI Analysis and Optimization of Thermal Issues in High Performance VLSI

Kaustav Banerjee Stanford University Massoud Pedram and Amir H. Ajami University of Southern California

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Presentation Outline Presentation Outline

Introduction Thermal Effects and Reliability Interconnect Performance Optimization High-Current Effects: ESD Analysis of Non-uniform Chip Temperature Non- Uniform Temperature Dependent Delay Circuit Optimization: Clock Skew Summary

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Introduction Introduction

Sources of chip power dissipation Chip temperature model Thermal effects in interconnects Scaling trends and implications

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Sources of Chip Power Dissipation Sources of Chip Power Dissipation

Dynamic Power: ∝ ∝ ∝ ∝ CV2f most significant Leakage Power: increasing with scaling C dominated by interconnects Affects interconnect temperature Dynamic Power: ∝ ∝ ∝ ∝ CV2f most significant Leakage Power: increasing with scaling C dominated by interconnects Affects interconnect temperature Devices: Close to Heat Sink Devices: Close to Heat Sink Interconnects: Away from Heat Sink Interconnects: Away from Heat Sink Joule Heating: I2R Joule Heating: I2R

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Chip Temperature Model Chip Temperature Model

• 1-D Heat Conduction

Heat Sink Package Si Substrate

Rn

TDie TO = 25 °C P/A

• TDie = 120 °C (180 nm Node)
• Rn = 4.75 cm2 °C/W
• +

+ + + = = = = A P R T T

n O Die

• Assuming same Packaging

and Cooling Technologies (Same Rn) TDie at Other Technology Nodes Calculated

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Thermal Effects in Interconnects Thermal Effects in Interconnects

An inseparable aspect of electrical power distribution and signal transmission through the interconnects Arise due to self-heating (or Joule heating) of interconnects caused by current flow Thermal effects impact interconnect electromigration reliability and design

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

∆ ∆ ∆ ∆T increases with increasing tox Self Heating under DC Stress (IRPS 96)

Thermal impedance θ θ θ θj, defined by ∆ ∆ ∆ ∆T = P x θ θ θ θj

100 200 300 400 500 600 1 2 3 4

Power [W] ∆ ∆ ∆ ∆T [0C]

M1 M3 M2 M4 M1: Metal1 M2: Metal2 M3: Metal3 M4: Metal4

increasing tox

Thickness of AlCu in M4 is doubled

L W= = = =1000 µ µ µ µ µ µ µ µ m 3 m TiN Silicon

θ θ θ θj

tox

AlCu

Oxide

Cross section

Thermal Effects in Interconnects Thermal Effects in Interconnects

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Impact of Scaling Using Low-k (IEDM 96)

Metal

SiO2 SiO2 Low-K (Gap Fill)

Metal

DC Conditions

As W decreases SH increases. Low-k increases SH by 10-15%

100 200 300 400 500 1 2 3

Power [W] ∆ ∆ ∆ ∆T [

0C]

Metal 1 Standard Dielectric 0.75 µm 1.5 µm 3 µm

Standard Dielectric

100 200 300 400 500 1 2 3

Power [W] ∆ ∆ ∆ ∆T [

0C]

Metal 1 Low-k Dielectric 0.75 µm 1.5 µm 3 µm

Low-K Dielectric

Thermal Effects in Interconnects Thermal Effects in Interconnects

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Scaling Effects (ITRS ’99) As Temperature Increases

Chip Power and Area increases Negligible Change in Power Density Current Density in Metal Lines Increases Number of Metal Levels Increases Electromigration (EM) Time to Failure Decreases Increased ρ ρ ρ ρ (T) Wire Delay Increases

Scaling Trends and Implications Scaling Trends and Implications

Chip Temperature Distribution ?

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2

Dielectric Constant (ε ε ε ε) Thermal Conductivity [W/m·K]

1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2

Dielectric Constant (ε ε ε ε) Thermal Conductivity [W/m·K]

Scaling Effects (1) :

Thermal Conductivity of Dielectrics

Scaling Effects (1) :

Thermal Conductivity of Dielectrics

( ITRS ’99 ) Air HSQ SiO2 Polyimide

180 nm 100 nm 100-130 nm 130 nm 70 nm <50 nm

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Full Chip Thermal Analysis Full Chip Thermal Analysis

• Three Dimensional Heat

Conduction

• Steady State, Uniform Heat

Generation (q’’’), Constant Properties (k)

,

2

= = = = ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ + + + + ∇ ∇ ∇ ∇ k q T

( Interconnect )

2

= = = = ∇ ∇ ∇ ∇ T

( Others )

• Worst Case Simulation

– Uniform jrms for all Metal Lines ( ITRS ’99 )

Si Substrate Si Substrate ILD ILD Cu IMD ILD ILD Interconnect Interconnect

x z y

TDie

q ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ P/A

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami
• Negligible

Change in Power Density

( ITRS ’99 )

• TDie = 133±15°C
• Increase in Tmax

Due to Joule Heating of Interconnects ( FEM Simulation )

Scaling Effects (2) :

Maximum Chip Temperature

Scaling Effects (2) :

Maximum Chip Temperature

50 100 150 200 250 180 130 100 70 50 35

Technology Node [nm] Temperature [°C]

0.0 0.2 0.4 0.6 0.8 1.0

Power Density [W/mm2]

Tmax TDie

50 100 150 200 250 50 100 150 200 250 180 130 100 70 50 35 180 130 100 70 50 35

Technology Node [nm] Temperature [°C]

0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0

Power Density [W/mm2]

Tmax TDie

(IEDM 2000)

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Scaling Effects (3) :

Temperature Distribution

Scaling Effects (3) :

Temperature Distribution

Temperature [°C]

100 nm 130 nm

180 nm

35 nm 70 nm

1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 120 140 160 180 200 220 120 140 160 180 200 220

Distance from Substrate [µ µ µ µm]

50 nm

50 nm Node

209 °C 126 °C

Global Wires Global Wires

(IEDM 2000)

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Scaling Effects (4) : Effects on

Reliability & Performance

Scaling Effects (4) : Effects on

Reliability & Performance

20 40 60 80 100 70 180 130 100 50 35

% Decrease in TTF Technology Node [nm]

20 40 60 80 100 20 40 60 80 100 70 180 130 100 50 35 70 180 130 100 50 35

% Decrease in TTF Technology Node [nm]

100 ) ( ) ( 1 %

max

× × × ×

• −

− − − = = = =

Die

T TTF T TTF TTF in D

10 20 30 40 50 180 130 100 70 50 35

% Increase in RC Delay Technology Node [nm]

10 20 30 40 50 10 20 30 40 50 180 130 100 70 50 35 180 130 100 70 50 35

% Increase in RC Delay Technology Node [nm]

100 1 ) ( ) ( %

max

× × × ×

• −

− − − = = = =

Die

T T Delay RC in I ρ ρ ρ ρ ρ ρ ρ ρ

(IEDM 2000)

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Scaling Trends and Implications (Summary) Scaling Trends and Implications (Summary)

Scaling trends that cause increasing thermal

effects: increasing interconnect levels increasing current density low-k dielectrics increasing thermal coupling

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Presentation Outline Presentation Outline

Introduction Thermal Effects and Reliability Interconnect Performance Optimization High-Current Effects: ESD Analysis of Non-uniform Chip Temperature Temperature Dependent Performance Circuit Optimization: Clock Skew Summary

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Electromigration (EM)

Transport of mass in metal interconnects under an applied current density EM lifetime reliability modeled using Black’s equation given by,

• =

= = =

− − − − m B n

T k Q exp j A TTF

TTF is the time-to-fail A is a constant that depends on line geometry and microstructure j is the DC or average current density Q is the activation energy for EM ( ~ 0.7 eV for AlCu) Tm is the metal temperature

Reliability Implications Reliability Implications

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Accelerated EM stress data yields A, Q, and n in Black’s equation, and a value of log-normal σ σ σ σLN Typical goal: achieve a 10 year lifetime EM stress data + Black’s equation gives a technology limit to the maximum allowed current density ( javg ) for the required failure rate and a desired lifetime at a reference temperature Tref ( ~ 100 0C) The javg limit does not comprehend self heating

Typical EM Analysis

Reliability Implications Reliability Implications

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Current Density Definitions (DAC 99)

Peak, Average, and RMS current densities: For an unipolar waveform: EM is determined by javg, and self-heating by jrms

A I j

peak peak =

= = =

( ( ( ( ) ) ) )dt

t j T j

T avg

• =

= = = 1

( ( ( ( ) ) ) )

• =

= = =

T rms

dt t j T j

2

1

A is the cross sectional area of interconnect, T is the time period of the current waveform.

T ton Ipeak Irms Iavg = I

DC

r =

ton/T

peak rms

j r j = = = =

peak avg

j r j = = = =

r is the duty factor

Reliability Implications Reliability Implications

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

EM lifetime given by:

Due to self-heating: Tm = Tref + ∆Tself-heating Impact of Self-Heating on EM (DAC 99)

• =

= = =

− − − − m B n

T k Q exp j A TTF

( ( ( ( ) ) ) )

θ θ θ θ

R R I T T T

rms ref m heating self 2

= = = = − − − − = = = = ∆ ∆ ∆ ∆

− − − −

Rθ

θ θ θ is the effective thermal impedance

given by,

eff ins ins

W L K t R = = = =

θ θ θ θ

Weff is the effective metal width to account for quasi-2D heat conduction.

Reliability Implications Reliability Implications

L

Silicon tins

Metal

insulator Wm Kins Tm Tref q tm

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Typically, design rules specify javg from EM and jrms from self-heating separately. Self-consistent approach: comprehends EM and self-heating simultaneously. The lifetime at any javg and metal temperature Tm, should be equal to or greater than the lifetime value (e.g., 10 year) under the design rule current density (j0).

Self-Consistent Design (Hunter 97)

2 ref B 2 avg m B

j T k Q exp j T k Q exp

• ≥

≥ ≥ ≥

• Reliability Implications

Reliability Implications

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Using the relationship between javg, jrms, jpeak and r for an unipolar waveform described earlier, it can be shown that, Incorporating the j2rms and j2avg values from yields the self-consistent equation,

Self-Consistent Equation

r j j

2 rms 2 avg =

= = =

( ( ( ( ) ) ) ) ( ( ( ( ) ) ) )

eff ins ref m m m m m ins ref B m B 2

W K T T T W t t T k Q exp T k Q exp j r − − − −

• =

= = = ρ ρ ρ ρ

This is a single equation in the single unknown temperature Tm

Reliability Implications Reliability Implications

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Reliability Implications Reliability Implications

1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09 0.0001 0.001 0.01 0.1 1

Duty Cycle r Maximum jrms [A/cm2]

1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09

Maximum jpeak [A/cm2]

Kins X 10-6 W/m0K 1.15 (SiO2) 0.60 (HSQ) 0.25 (Polyimide k) 0.024 (Air)

Low-k/Cu: Implications for Current Density Limits

• Self-consistent jrms and jpeak decrease significantly as low-k

materials are introduced.

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Reliability Implications Reliability Implications

Implications for Interconnect Technology

• As r decreases, material changes (increasing j0) will become

ineffective in increasing jpeak.

100 200 300 400 500 600 700 800 0.0001 0.001 0.01 0.1 1

Duty Cycle r Self-Consistent Metal Temperature Tm [0C]

1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09

Maximum jpeak [A/cm2] Air j0 X 105 A/cm2

6.0 9.0 13.5 20.3

SiO2 SiO2

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Reliability Implications Reliability Implications

Implications for Current Density Limits

Comparison with AlCu

1 2 3 4 5 6 7 Oxide HSQ Polyimide Air

Dielectric Maximum Allowed j peak (MA/cm

2)

Cu: javg = 1.8 MA/cm2 Cu: javg = 0.6 MA/cm2 AlCu: javg = 0.6 MA/cm2

0.1-µm/Metal 8 r = 0.1

• Thermal effects reduce the advantage of Cu as low-k

materials are introduced

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Presentation Outline Presentation Outline

Introduction Thermal Effects and Reliability Interconnect Performance Optimization High-Current Effects: ESD Analysis of Non-uniform Chip Temperature Temperature Dependent Performance Circuit Optimization: Clock Skew Summary

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Thermal effects predominant in semi-global and global interconnects which are: Away from the Si substrate Long Typically split into buffered segments Long interconnects can be optimally buffered.

Semi-Global and Global Wires

sopt s lopt

Performance Optimization Performance Optimization

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Performance Based Current Density (Signal Lines)

• jrms (max) occurs close to the repeater output due to the

distributed nature of the interconnect.

0.25 µ µ µ µm and 0.1 µ µ µ µm technology Full 3-D Interconnect capacitance extracted Accurate lopt and sopt values determined by SPICE simulations

jrms (max)

sopt sopt lopt

Performance Optimization Performance Optimization

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Effect of Thermal coupling Included (NTRS Based)

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Oxide HSQ Polyimide Air

Dielectric javg [x105 A/cm 2]

Performance Reliability Reliability-Multilevel

0.1-µm/Metal 8

• For point-to-point interconnects reliability design limits satisfied

even after considering thermal coupling

Performance vs Reliability Performance vs Reliability

Gets Worse for ITRS Data

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Presentation Outline Presentation Outline

Introduction Thermal Effects and Reliability Interconnect Performance Optimization High-Current Effects: ESD Analysis of Non-uniform Chip Temperature Temperature Dependent Performance Circuit Optimization: Clock Skew Summary

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Electrostatic Discharge (ESD) A short duration (< 200 ns), high current (> 1 A) event Can cause open circuit failure of metals and latent damage that impact EM reliability

High-Current Effects High-Current Effects

Non Steady-State Scenarios Non Steady-State Scenarios

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Failure current densities are much higher than under normal circuit conditions

1 2 3 4 2 4 6 8

Current Density, J [x107 A/cm2] Resistance Rise, ∆Rmax/R0

200 400 600 800 1000 1200

Temperature Rise, ∆Tmax [0C]

Metal 1 Metal 2 Metal 3 Metal 4

∆t = 200 ns

γcrit

Melt Threshold

Self-heating characteristics of AlCu lines under short- pulse stress conditions (Electron Device Letters 97)

• Metal 1, 2, & 3 show

identical SH

• Higher SH in Metal 4 is

due to smaller surface area to volume ratio

• Interconnect failure

temperature is ~ 1000 0C

Non Steady-State Self-Heating Non Steady-State Self-Heating

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Open Circuit Failure (IRPS 2000)

• Passivation fracture due to the expansion of critical volume
• f molten AlCu. (@ 1000 0C)
• Independent of overlying dielectric thickness.

Metal 4 ~ 12 µ µ µ µm Metal 1 ~ 12 µ µ µ µm

High-Current Effects High-Current Effects

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Significant Electromigration Performance Degradation

1 µ µ µ µm 0.15 µ µ µ µm Unstressed AlCu Stressed AlCu

Latent Interconnect Damage (IRPS 2000)

High-Current Effects High-Current Effects

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Summary (1) Summary (1)

Thermal Analysis including Interconnect Joule Heating based on ITRS ’99

Peak Temperatures in ICs Increase with Technology Scaling in Spite of Constant Power Density Significant Implications for Performance and Reliability Advanced Chip Cooling Techniques may be Necessary

Thermal Effects and Reliability

Thermal Effects Strongly Impacts EM Self-Consistent Analysis: Thermal + EM Point-to-Point Interconnects Optimized for Performance Meets Reliability Based Current Density Limits High-Current Design Rules Must be Followed for I/O and ESD Protection Circuit Interconnects

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Presentation Outline Presentation Outline

Introduction Thermal Effects and Reliability Interconnect Performance Optimization High-Current Effects: ESD Analysis of Non-uniform Chip Temperature Temperature Dependent Performance Circuit Optimization: Clock Skew Summary

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Interconnect Temperature Interconnect Temperature

L tox tm

Interconnect Oxide

Via Via

Substrate

(Tref )

(Tline )

Heat equation in Interconnect (DAC 2001)

2 2 line m

d T Q dx k = −

2 2 2 2

( ) ( ) ( )

line line ref

d T x T x T x dx λ λ θ = − −

λ λ λ λ and θ θ θ θ are constants

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Solution to Heat Equation Solution to Heat Equation

200 400 600 800 1000 1200 1400 1600 1800 2000

108 109 110 111 112 113 114 115 116 117

Position x (micron)

Thermal profile for different technology nodes

T(x) (c)

• Tech. node 0.1 micron
• Tech. node 0.25 micron

d

d

Tref = 100 °C

T(x=0) = 100 °C T(x=2000) = 100 °C

L=2000 µ µ µ µm

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Non-Uniform Substrate Temperature Non-Uniform Substrate Temperature

Due to different switching activities, substrate temperature is generally non- uniform.

DPM, Functional block clock gating Thermal time constant is much higher that signal propagation constant

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Presentation Outline Presentation Outline

Introduction Thermal Effects and Reliability Interconnect Performance Optimization High-Current Effects: ESD Analysis of Non-uniform Chip Temperature Temperature Dependent Performance Circuit Optimization : Clock Skew Summary

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Non-uniform Interconnect Thermal Profile Non-uniform Interconnect Thermal Profile

Long global interconnects span large area

Experience substrate thermal non- uniformity with high probability Assuming a uniform substrate thermal profile results in delay estimation errors

Introduces error in wire-planning and

• ptimization steps

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Temperature Dependence of Resistance Temperature Dependence of Resistance

Resistance is dependent on Temeprature ρ ρ ρ ρ0 is the resistance per unit length at reference temperature β β β β is the temperature coefficient of resistance (1/°C) Non-Uniform line temperature

• non-

uniform resistance profile

Unit length capacitance is not affected

( ) (1 ( )) r x T x ρ β = + ⋅

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Non-Uniform Temperature Dependent Delay Non-Uniform Temperature Dependent Delay

Distributed RC delay model (DAC 2001)

∆ ∆ ∆ ∆x rd CL L

( ( ) ) ( )( ( ) )

L L L d L L x

D R C c x dx r x c d C dx τ τ = + + +

• (

) ( ) ( )

L L L

D D c L C T x dx c xT x dx ρ β ρ β = + + −

• D0 is the Elmore delay model at 0 °

° ° °C

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Delay Degradation with Uniform Tref(x) Delay Degradation with Uniform Tref(x)

With uniform thermal profile (0.25 µ

µ µ µm): 5-6% increase for each 20-degree increase in long global lines

5 10 15 20 25 30 35 40 45 50 30 50 70 90 110 130 150 Temperature ( C ) Delay Increase (%) L=100 L=400 L=700 L=1000 L=2000

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Effect of exponential thermal profiles:

200 400 600 800 1000120014001600 18002000 20 40 60 80 100 120 140 160 180 200

Position (X)

T(x) Exponential Thermal Profile TH TL

8 10 12 14 16 18 20 22 24 30 50 70 90 110 130

P e a k Te m pe ra ture ( C )

L=2000,T1 L=1000,T1 L=2000,T2 L=1000,T2

TL=30 °C

Delay Degradation with Non-uniform Tref(x) Delay Degradation with Non-uniform Tref(x)

Direction of Thermal Gradient is Important

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Directional Thermal Profile Directional Thermal Profile

Increasing (decreasing) thermal profile is equivalent to decreasing (increasing) sizing profile for uniform resistance wire Increasing thermal profile has better performance than that of decreasing thermal profile (optimal wire sizing)

T(x) T(x) T(x) T(x) x x x x

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Presentation Outline Presentation Outline

Introduction Thermal Effects and Reliability Interconnect Performance Optimization High-Current Effects: ESD Analysis of Non-uniform Chip Temperature Temperature Dependent Performance Circuit Optimization : Clock Skew Summary

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Clock Net Routing Clock Net Routing

Clock is the most vulnerable signal to the underlying thermal non-uniformity

Have long global segments in the highest metal layers delay variations affect skew

Clock nets must have near-zero skew among their sinks to guarantee correct functionality of the circuits

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

H-Tree’s H-Tree’s

H-Tree or bottom-up merging techniques Balancing loads seen at merging point in H-Tree to have zero-skew at two sides of each branch

1 2 2 3 3 3 3

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Branching Point (CICC 2001) Branching Point (CICC 2001)

Equal load at each sink: middle point is the branching point (l) With non-uniform thermal profile, branching point dependent on the profile

l L-l

p

q x 1 2 2

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Branching Point cont’d Branching Point cont’d

Using thermally dependent delay, optimal branching location (l*) is: With symmetric non-uniform thermal profile, the branching point is still at l*=L/2

*

*

( )

l

T x dx l A β + − =

• A is constant

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Movement of Branching Point Movement of Branching Point

In gradually decreasing (increasing) thermal profile, optimal length l* has to be less than (greater than) L/2.

T(x) T(x) T(x) T(x) x x x x L/2 L/2 L/2 L/2

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Thermally Dependent Merging Thermally Dependent Merging

Thermal non-uniformity can introduce a significant skew in the clock tree Thermally-dependent bottom-up merging must be used to minimize the skew

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Results (CICC 2001) Results (CICC 2001)

9.57 911

µ µ µ µ=300, σ σ σ σ=700

0.0 1000

µ µ µ µ=1000, σ σ σ σ=400

2.40 979.5

TH=170, TL=130

3.63 968.66

TH=170, TL=110

2.65 1021

TH=170, TL=130

3.98 1032

TH=170, TL=110

5.42 1042 TH=170, TL=90 7.78 1210

µ µ µ µ=2000, σ σ σ σ=1000

5.24 957.5

TH=170, TL=90

( ) T x ax b = +

H L

T T a L − =

L

b T = ( )

bx

T x a e− = ⋅

H

a T =

1 ln( )

H L

T b L T =

2 2

( ) 2 m ax

( )

x

T x T e

µ σ − − −

= ⋅

l=L/2 skew%

l=l* params Tline(x)

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Effects of Non-Uniform Temeprature on EDA Flow Effects of Non-Uniform Temeprature on EDA Flow

Interconnect non-uniform thermal profile can affect many EDA flow steps

Optimal layer assignment Buffer insertion Wire sizing Gate sizing

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Summary (2) Summary (2)

Impact of Non-Uniform Substrate Temperature Different switching activities in the substrate cause thermal gradients Interconnect temperature is strongly dependent on substrate thermal profile As technology scales, effect of substrate temperature becomes more important

ISPD 2001 ISPD 2001

• K. Banerjee, M. Pedram and A. H. Ajami

Summary (2) Summary (2)

Performance dependency

Delay model for non-uniform line temperature presented Delay based on uniform worst case line temperature is not sufficient Direction of thermal gradients is important

Signal Integrity : Clock Skew

Non-uniform substrate temperature introduces skew in the clock tree Bottom-up merging techniques must consider non- uniform interconnect thermal profile Skew can be minimized by suitable merging