Analog/Digital Control Methods Instructor: Fionn Sheerin, Senior - - PowerPoint PPT Presentation

Analog and Hybrid Analog/Digital Control Methods

Instructor:

Fionn Sheerin, Senior Product Marketing Engineer, Microchip Technology, Inc.

HOUSEKEEPING

• Housekeeping
• Presentation
• Text Chat Questions and Answers
• Wrap-up

3

Agenda

 Analog Control

 System and control loop operation  Voltage and current mode control methods  Design and circuit example

 Hybrid Analog / Digital Control

 Digital management of analog control loops

 Track 3: Full Digital System Control

4

SMPS Loop Closure

 Why “close the loop”?

 Feedback control determines the

performance of the SMPC in terms of line regulation, load regulation, and dynamic response

 Better control

5

Switching Regulators

 Switching regulators monitor the input voltage, output

voltage, switch or inductor current in order to adjust the switch duty cycle in response to line and load changes

Vin Vout +

• Control

Vin Vout +

• Control

Synchronous Buck Circuit Asynchronous Boost Circuit

6

Control Loops

7

Analog SMPC Loop Closure

VS VO IO IS VS-VO VO v1 iL vL iS DT D2T T T RLOAD VO D1 v1 C1 L1 VS + Q1

Buck converter

8

RLOAD VO C1 L1 VS + Q1

Switch conducting (DT)

v1

Analog SMPC Loop Closure

VS VO IO IS VS-VO VO v1 iL vL iS DT D2T T T RLOAD VO D1 v1 C1 L1 VS + Q1

Buck converter

9

RLOAD VO C1 L1 VS + Q1

Switch conducting (DT)

v1 RLOAD VO D1 v1 C1 L1 VS +

Diode conducting (D2T)

Analog SMPC Loop Closure

VS VO IO IS VS-VO VO v1 iL vL iS DT D2T T T RLOAD VO D1 v1 C1 L1 VS + Q1

Buck converter

10

RLOAD VO C1 L1 VS + Q1

Switch conducting (DT)

v1 RLOAD VO D1 v1 C1 L1 VS +

Diode conducting (D2T)

Analog SMPC Loop Closure

VS VO IO IS VS-VO VO v1 iL vL iS DT D2T T T RLOAD VO D1 v1 C1 L1 VS + Q1

Buck converter

11

Analog SMPC Loop Closure

System Output Input

12

Analog SMPC Loop Closure

System Output Input

Feedback Reference Error

13

Analog SMPC Loop Closure

System Output Input

Feedback Feedforward Reference Error

14

Analog SMPC Loop Closure

Output

G

u Reference ur Inputs e

r

u G u  

15

Analog SMPC Loop Closure

H

Negative Feedback Output

G

u Reference ur Inputs e

GH G r u u   1 H r u u 1 

If G is much bigger than one (large

• pen loop gain)

16

Analog SMPC Loop Closure

Feedforward

PowerSystem

Power Circuitry e Input u Output Control Circuitry d Control ur Reference Feedback

17

Analog SMPC Loop Closure

KPWR KLC KMOD Control

• r

Reference VS VO + KEA(S) Error Amplifier with compensation KMOD Pulse width modulator KPWR Power switching topology KLC(S) Output power filter KFB Feedback T(s) = KEA(S)* KMOD* KPWR* KLC(S)* KFB Open-loop gain KEA KFB

18

SMPS Control Methods

 Voltage mode control

 Output voltage feedback into transfer function

to adjust duty cycle

 Voltage mode control with feedforward

 Output and input voltages feed into transfer

function to adjust duty cycle

 Current mode control

 Inductor current and output voltage feed into

transfer function to adjust duty cycle

19

SMPS Control Methods

VS VO v1 VC D DT T T VO D VS + v1

KFB KEA PWM Comp

+ -

• +

VC

DIRECT DUTY CYCLE CONTROL (VOLTAGE MODE CONTROL)

VRAMP

VREF

20

SMPS Control Methods

VS VO v1 VC D DT T T VO D VS + v1

KFB KEA PWM Comp

+ -

• +

VC

DIRECT DUTY CYCLE CONTROL (VOLTAGE MODE CONTROL)

VRAMP

VREF

21

SMPS Control Methods

VS VO v1 iS D1 Q DT T T VO D VS + v1

KFB KEA PWM Comp

+ -

• +

VC

PEAK CURRENT MODE CONTROL

VC

VREF

Clock S

22

 Subharmonic

instability

Waveforms of Subharmonic Instability

iL D DT T T VC

Clock S

IS iL DT T VC

Clock S

IS

 Stable

• peration

D T m1 m2

23

Adding Stabilizing Ramp

VO D VS + v1

KFB KEA PWM Comp

+ -

• +

VC

VREF

Clock

R S Q

24

SMPS Control Methods

 Voltage Mode

 Single feedback loop  Good noise immunity  Good cross regulation for

multiple outputs

 Poor dynamic response  Error amplifier must

account for double pole LC in CCM (complex conjugate poles)

 Loop gain varies with

input voltage

 Current Mode

 Two feedback loops  Poor noise immunity  Good line response and

gain constant

 Load regulation worse  Single pole  Inherent pulse-by-pulse

current limiting

 Requires slope

compensation (ramp)

25

SMPC Loop Closure

 Loop Design Procedure

 Define the control loop strategy and plot the

tentative goal

 Plot the known part of the loop Bode plot of KMOD* KPWR* KLC(S)* KFB  Define the crossover frequency  Design and plot the error amplifier

compensation network

26

Error Amplifier Compensation Example

DC Analysis

VO D VS + CR L C R

Buck - Continuous Inductor Current - Direct Duty Cycle Control

S RAMP O C RAMP C S S O RAMP C

V V V V V V V D V V V V D    

Voltage Time VRamp VC

27

Error Amplifier Compensation Example

Control to Output Transfer Function DC Analysis

VO D VS + CR L C R

Buck - Continuous Inductor Current - Direct Duty Cycle Control

S RAMP O C RAMP C S S O RAMP C

V V V V V V V D V V V V D    

L R Q C R LC s Q s s s H s H V V v v

O ESR Z O O O Z e e RAMP S C O

              1 1 ) ( ) ( 1 1 ) ( ) (

2

Voltage Time VRamp VC

28

Error Amplifier Compensation Example

Design Example

VO D VS + CR L C R

Buck - Continuous Inductor Current - Direct Duty Cycle Control

V V m R F C H L D R A A I V V V V V S T kHz f

RAMP ESR O O S S

5 . 2 100 15 15 25 . to 5 . 1 to 5 5 to 1 5 20 to 10 2 500                 

29

Error Amplifier Compensation Example

Design Example

VO D VS + CR L C R

Buck - Continuous Inductor Current - Direct Duty Cycle Control

V V m R F C H L D R A A I V V V V V S T kHz f

RAMP ESR O O S S

5 . 2 100 15 15 25 . to 5 . 1 to 5 5 to 1 5 20 to 10 2 500                 

kHz C R f kHz LC f

ESR Z O

106 2 1 6 . 10 2 1       Calculate System Poles and Zeros

30

Error Amplifier Compensation Example

Design Example

VO D VS + CR L C R

Buck - Continuous Inductor Current - Direct Duty Cycle Control

V V m R F C H L D R A A I V V V V V S T kHz f

RAMP ESR O O S S

5 . 2 100 15 15 25 . to 5 . 1 to 5 5 to 1 5 20 to 10 2 500                 

kHz C R f kHz LC f

ESR Z O

106 2 1 6 . 10 2 1       Calculate System Poles and Zeros V dB V dB V V v v

RAMP S C O

10 at ) 12 ( 4 20 at ) 18 ( 8    Calculate Low Frequency Gain

31

Error Amplifier Compensation Example

Crossover Frequency Goal: Buck - Continuous Inductor Current - Direct Duty Cycle Control

kHz kHz f f

S C

125 4 500 4   

kHz kHz f f

O Z

3 . 5 2 6 . 10 2   

Two second order filter poles at fo are compensated by two zeros at fo /2. This provides additional phase shift at fo for sudden second order transition. ESR zero is compensated by a pole at least a decade above the two zeros. E/A Gain Needed at Crossover:

dB f f f f

Z C O Z

4 . 23 ) log( 20 ) log( 40 18    

kHz fP 53 

32

Error Amplifier Compensation Example

• 30
• 20
• 10

10 20 30 40 50 60 0.1 1 10 100 1000 Frequency (kHz) Gain (dB)

Blue – Uncompensated Transfer Function Red – Compensation Network Green – Final System

33

Error Amplifier Compensation Example

VO

KFB PWM Comp KEA

• +

VC

VREF

• +

R11 R12 R1 R2 C1 C2 C3

D Error amplifier Three Poles and Two Zeros wZ1 = 1 / (C1 * R1) wZ2 = 1 / (C2 * R2) wP0 = 0 wP1 = 1 / (C1 * (R1 || R11) wP2 = 1 / (R2 * (C2 || C3) Pulse width modulator and Feedback gains KMOD = d / vC = 1 / VRAMP KMODX = d / vC = D / VRAMP = VO / (VS* VRAMP) KFB = VO / VREF = R12 / (R11 + R12)

34

PWM Controller System Example

VOUT VIN= 5-30V 5V, 25mA

GND VIN LOWDR LDO PWRGD BOOT

MCP19035

HIGHDR PHASE FB COMP SHDN

35

PWM Controller System Example

VOUT VIN= 5-30V 5V, 25mA

GND VIN LOWDR LDO PWRGD BOOT

MCP19035

HIGHDR PHASE FB COMP SHDN

Analog Compensation Network

36

Hybrid Analog / Digital Methods

37

Summary

 Discrete DC-DC implementations require

loop closure, adding substantial design complexity compared to integrated solutions

 Same as integrated solutions: good regulator

selection, passive component selection, and layout are required

 Digital features can be implemented in an

analog control system

 Highest efficiency, highest performance

systems require digital control

 Track 3: Digital Power Control

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Instructor: Fionn Sheerin, Senior Product Marketing Engineer, Microchip Technology, Inc. Moderator: Rich Nass, EVP, OpenSystems Media

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