Advanced SAT-Techniques for Bounded Model Checking of Blackbox - PowerPoint PPT Presentation

Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs Marc Herbstritt (joint work with Bernd Becker and Christoph Scholl) Institute of Computer Science Albert-Ludwigs-University Freiburg im Breisgau, Germany Presentation at IEEE MTV 2006, Dec 04 2006 www.avacs.org

Overview Introduction 1 Blackbox BMC using 01X-Logic 2 Example Basic algorithm Improvements Experimental Results Blackbox BMC using QBF 3 Example Basic modelling Additional Constraints Final QBF Formula Experimental Results Conclusions 4

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Background Formal Verification of Circuits → Checking correctness between specification and implementation Model Checking → Specification given by a set of (temporal) properties → Model Checking to prove that circuit model fulfills the properties → Bounded Model Checking to falsify properties Blackbox Designs → describe partial circuit implementations → occur naturally in early design phase → can be used for abstraction, e.g. in diagnosis This work: → Bounded Model Checking of Blackbox Designs (BB-BMC) → Improving BB-BMC based on 01X-logic → More concise formulation for BB-BMC using QBF

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Background Formal Verification of Circuits → Checking correctness between specification and implementation Model Checking → Specification given by a set of (temporal) properties → Model Checking to prove that circuit model fulfills the properties → Bounded Model Checking to falsify properties Blackbox Designs → describe partial circuit implementations → occur naturally in early design phase → can be used for abstraction, e.g. in diagnosis This work: → Bounded Model Checking of Blackbox Designs (BB-BMC) → Improving BB-BMC based on 01X-logic → More concise formulation for BB-BMC using QBF

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Background Formal Verification of Circuits → Checking correctness between specification and implementation Model Checking → Specification given by a set of (temporal) properties → Model Checking to prove that circuit model fulfills the properties → Bounded Model Checking to falsify properties Blackbox Designs → describe partial circuit implementations → occur naturally in early design phase → can be used for abstraction, e.g. in diagnosis This work: → Bounded Model Checking of Blackbox Designs (BB-BMC) → Improving BB-BMC based on 01X-logic → More concise formulation for BB-BMC using QBF

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Background Formal Verification of Circuits → Checking correctness between specification and implementation Model Checking → Specification given by a set of (temporal) properties → Model Checking to prove that circuit model fulfills the properties → Bounded Model Checking to falsify properties Blackbox Designs → describe partial circuit implementations → occur naturally in early design phase → can be used for abstraction, e.g. in diagnosis This work: → Bounded Model Checking of Blackbox Designs (BB-BMC) → Improving BB-BMC based on 01X-logic → More concise formulation for BB-BMC using QBF

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Applications of Blackbox Designs: ISCAS c3540 Shifter A MUX MUX B MUX BCD−SUB BCD−ADD ALU MUX C3540: ALU with binary and BCD arithmetic, logic and shift operations. (Source: Hansen, Yalcin, Hayes − Unveiling the ISCAS85 Benchmarks, IEEE Design&Test, 1999) Abstraction: Hide components that are not necessary 1 Verification of Partial Designs: E.g. in early design stage 2 Error Diagnosis: Localisation of error 3

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Applications of Blackbox Designs: ISCAS c3540 op(A,B,+,bin) = enc(A,bin) + enc(B,bin) ? Shifter A MUX MUX B MUX BCD−SUB BCD−ADD ALU MUX Abstraction: Hide components that are not necessary 1 Verification of Partial Designs: E.g. in early design stage 2 Error Diagnosis: Localisation of error 3

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Applications of Blackbox Designs: ISCAS c3540 op(A,B,+, ) = bin enc(A, ) + enc(B, ) ? bin bin Blackbox A MUX MUX B MUX Blackbox Blackbox ALU Property is not dependent MUX on BCD−units and Shifter, but only on encoding binary Abstraction: Hide components that are not necessary 1 Verification of Partial Designs: E.g. in early design stage 2 Error Diagnosis: Localisation of error 3

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Applications of Blackbox Designs: ISCAS c3540 op(A,B,+,bin) = enc(A,bin) + enc(B,bin) ? Blackbox A MUX MUX B MUX Blackbox BCD−ADD ALU Implementation of Shifter and MUX BCD−SUB unit not finished Abstraction: Hide components that are not necessary 1 Verification of Partial Designs: E.g. in early design stage 2 Error Diagnosis: Localisation of error 3

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Applications of Blackbox Designs: ISCAS c3540 Shifter A MUX MUX B Blackbox MUX BCD−SUB ALU MUX Check whether error lies within the blackbox region Abstraction: Hide components that are not necessary 1 Verification of Partial Designs: E.g. in early design stage 2 Error Diagnosis: Localisation of error 3

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Blackbox BMC using 01X-Logic: Example Y q0 p Black− box q1 q ′ q ′ 0 = q 0 + y + Z 1 = q 0 + q 1 p = q 0 ⊕ q 1 Property: AG ( ¬ p )

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Blackbox BMC using 01X-Logic: Example Y q0 X 0 p Black− box 0 q1 1 step y q 0 q 1 p 0 — 0 1 0

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Blackbox BMC using 01X-Logic: Example 1 Y q0 X 1 p Black− box 0 q1 1 step y q 0 q 1 p 0 — 0 1 0 1 1 1 1 0

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions Blackbox BMC using 01X-Logic: Example 0 Y q0 X 1 p Black− box 1 q1 1 step y q 0 q 1 p 0 — 0 1 0 1 1 1 1 0 2 0 1 1 1

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions 01X-BB-BMC: Basics Blackbox outputs are unknown 1 ⇒ use logical value X , i.e., X = unknown whether 0 or 1 ⇒ use additional variable Z , and assign Z = X 01X-Logic 2 NOT 01X ( a ) AND 01X ( a , b ) a b 0 1 X 0 1 a 1 0 0 0 0 0 X X 1 0 1 X X 0 X X Deciding satisfiability for 01X-BB-BMC (see Herbstritt et 3 al. MTV’05) integrate deduction rules of 01X-logic at high-level into 1 structural SAT-solver: ( f = g · h , g = 1 , h = X ) ⇒ f = X , or apply two-valued encoding and solve purely propositional 2 SAT problem

Introduction Blackbox BMC using 01X-Logic Blackbox BMC using QBF Conclusions 01X-BB-BMC: Two-valued encoding Two-valued encoding for 01X-Logic (see Jain et al. VTS’00) Mapping of 01X-values to tuples of propositional values 01X-value z encoding ( z 0 , z 1 ) 0 (1,0) 1 (0,1) X (0,0) Synthesis transformation using propositional operations only ⇒ NOT 01X ( a ) = [ a 1 , a 0 ] ⇒ AND 01X ( a , b ) = [ a 0 + b 0 , a 1 · b 1 ] Transformation preserves uniform encoding of value X