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ADVANCED DATABASE SYSTEMS Index Locking & Latching @ - - PowerPoint PPT Presentation

Lect ure # 06 ADVANCED DATABASE SYSTEMS Index Locking & Latching @ Andy_Pavlo // 15- 721 // Spring 2019 CMU 15-721 (Spring 2019) 2 TO DAY'S AGEN DA Index Locks vs. Latches Latch Implementations Index Latching (Logical) Index Locking


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SLIDE 1

Index Locking & Latching

@ Andy_Pavlo // 15- 721 // Spring 2019

ADVANCED DATABASE SYSTEMS

Lect ure # 06

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SLIDE 2 CMU 15-721 (Spring 2019)

TO DAY'S AGEN DA

Index Locks vs. Latches Latch Implementations Index Latching (Logical) Index Locking (Physical)

2

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SLIDE 3 CMU 15-721 (Spring 2019)

DATABASE IN DEX

A data structure that improves the speed of data retrieval operations on a table at the cost of additional writes and storage space. Indexes are used to quickly locate data without having to search every row in a table every time a table is accessed.

3

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SLIDE 4 CMU 15-721 (Spring 2019)

DATA STRUCTURES

Order Preserving Indexes

→ A tree-like structure that maintains keys in some sorted

  • rder.

→ Supports all possible predicates with O(log n) searches.

Hashing Indexes

→ An associative array that maps a hash of the key to a particular record. → Only supports equality predicates with O(1) searches.

4

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SLIDE 5 CMU 15-721 (Spring 2019)

B- TREE VS. B+ TREE

The original B-tree from 1972 stored keys + values in all nodes in the tree.

→ More memory efficient since each key only appears once in the tree.

A B+tree only stores values in leaf nodes. Inner nodes only guide the search process.

→ Easier to manage concurrent index access when the values are only in the leaf nodes.

5

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SLIDE 6 CMU 15-721 (Spring 2019)

O BSERVATIO N

We already know how to use locks to protect

  • bjects in the database.

But we have to treat indexes differently because the physical structure can change as long as the logical contents are consistent.

6

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SLIDE 7 CMU 15-721 (Spring 2019)

SIM PLE EXAM PLE

7

A

K0 K2

Txn #1:

READ(K2)

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SLIDE 8 CMU 15-721 (Spring 2019)

SIM PLE EXAM PLE

7

A

K0 K2

Txn #2: Txn #1:

INSERT(K1) READ(K2)

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SLIDE 9 CMU 15-721 (Spring 2019)

SIM PLE EXAM PLE

7

A

K0 K2

B

K0 K2

C Txn #2: Txn #1:

INSERT(K1) READ(K2)

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SLIDE 10 CMU 15-721 (Spring 2019)

SIM PLE EXAM PLE

7

A

K0 K2

B

K0 K2

C Txn #2:

K1 K1 K2

Txn #1:

INSERT(K1) READ(K2)

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SLIDE 11 CMU 15-721 (Spring 2019)

SIM PLE EXAM PLE

7

A

K0 K2

B

K0 K2

C Txn #2:

K1

Txn #1:

K1 K2

Txn #1:

INSERT(K1) READ(K2) READ(K2)

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SLIDE 12 CMU 15-721 (Spring 2019)

LO CKS VS. LATCH ES

Locks

→ Protects the index’s logical contents from other txns. → Held for txn duration. → Need to be able to rollback changes.

Latches

→ Protects the critical sections of the index’s internal data structure from other threads. → Held for operation duration. → Do not need to be able to rollback changes.

8

A SURVEY OF B- TREE LOCKING TECHNIQUES

TODS 2 2010

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SLIDE 13 CMU 15-721 (Spring 2019)

LO CKS VS. LATCH ES

9

Locks Latches

Separate… User transactions Threads Protect… Database Contents In-Memory Data Structures During… Entire Transactions Critical Sections Modes… Shared, Exclusive, Update, Intention Read, Write Deadlock Detection & Resolution Avoidance …by… Waits-for, Timeout, Aborts Coding Discipline Kept in… Lock Manager Protected Data Structure

Source: Goetz Graefe

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SLIDE 14 CMU 15-721 (Spring 2019)

LO CK- FREE IN DEXES

Possibility #1: No Locks

→ Txns don’t acquire locks to access/modify database. → Still have to use latches to install updates.

Possibility #2: No Latches

→ Swap pointers using atomic updates to install changes. → Still have to use locks to validate txns.

10

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SLIDE 15 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Blocking OS Mutex Test-and-Set Spinlock Queue-based Spinlock Reader-Writer Locks

11

Source: Anastasia Ailamaki

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SLIDE 16 CMU 15-721 (Spring 2019)

CO M PARE- AN D- SWAP

Atomic instruction that compares contents of a memory location M to a given value V

→ If values are equal, installs new given value V’ in M → Otherwise operation fails

12

M

__sync_bool_compare_and_swap(&M, 20, 30)

20

Compare Value Address New Value

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SLIDE 17 CMU 15-721 (Spring 2019)

CO M PARE- AN D- SWAP

Atomic instruction that compares contents of a memory location M to a given value V

→ If values are equal, installs new given value V’ in M → Otherwise operation fails

12

M

__sync_bool_compare_and_swap(&M, 20, 30)

30

Compare Value Address New Value

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SLIDE 18 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #1: Blocking OS Mutex

→ Simple to use → Non-scalable (about 25ns per lock/unlock invocation) → Example: std::mutex

13

std::mutex m; ⋮ m.lock(); // Do something special... m.unlock(); pthread_mutex_t

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SLIDE 19 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #2: Test-and-Set Spinlock (TAS)

→ Very efficient (single instruction to lock/unlock) → Non-scalable, not cache friendly → Example: std::atomic<T>

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std::atomic_flag latch; ⋮ while (latch.test_and_set(…)) { // Yield? Abort? Retry? }

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SLIDE 20 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #2: Test-and-Set Spinlock (TAS)

→ Very efficient (single instruction to lock/unlock) → Non-scalable, not cache friendly → Example: std::atomic<T>

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std::atomic_flag latch; ⋮ while (latch.test_and_set(…)) { // Yield? Abort? Retry? }

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SLIDE 21 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch

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SLIDE 22 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch CPU1

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SLIDE 23 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch CPU1

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SLIDE 24 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch CPU1

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SLIDE 25 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch CPU1

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SLIDE 26 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch next CPU2 Latch CPU1 CPU2

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SLIDE 27 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch next CPU2 Latch CPU1 CPU2

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SLIDE 28 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch next CPU2 Latch CPU1 CPU2

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SLIDE 29 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch next CPU2 Latch CPU1 CPU2

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SLIDE 30 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch next CPU2 Latch CPU1 CPU2 CPU3 next CPU3 Latch

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SLIDE 31 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch next CPU2 Latch CPU1 CPU2 CPU3 next CPU3 Latch

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SLIDE 32 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #3: Queue-based Spinlock (MCS)

→ More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic<Latch*>

15

next Base Latch next CPU1 Latch next CPU2 Latch CPU1 CPU2 CPU3 next CPU3 Latch

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SLIDE 33 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

16

read write Latch

=0 =0 =0 =0

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SLIDE 34 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

16

read write Latch

=0 =0 =0 =0

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SLIDE 35 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

16

read write Latch

=0 =0 =0 =0 =1

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SLIDE 36 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

16

read write Latch

=0 =0 =0 =0 =1

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SLIDE 37 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

16

read write Latch

=0 =0 =0 =0 =1 =2

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SLIDE 38 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

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read write Latch

=0 =0 =0 =0 =1 =2

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SLIDE 39 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

16

read write Latch

=0 =0 =0 =0 =1 =2 =1

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SLIDE 40 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

16

read write Latch

=0 =0 =0 =0 =1 =2 =1

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SLIDE 41 CMU 15-721 (Spring 2019)

LATCH IM PLEM EN TATIO NS

Choice #4: Reader-Writer Locks

→ Allows for concurrent readers → Have to manage read/write queues to avoid starvation → Can be implemented on top of spinlocks

16

read write Latch

=0 =0 =0 =0 =1 =2 =1 =1

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SLIDE 42 CMU 15-721 (Spring 2019)

LATCH CRABBIN G / CO UPLIN G

Acquire and release latches on B+Tree nodes when traversing the data structure. A thread can release latch on a parent node if its child node considered safe.

→ Any node that won’t split or merge when updated. → Not full (on insertion) → More than half-full (on deletion)

17

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SLIDE 43 CMU 15-721 (Spring 2019)

LATCH CRABBIN G

Search: Start at root and go down; repeatedly,

→ Acquire read (R) latch on child → Then unlock the parent node.

Insert/Delete: Start at root and go down,

  • btaining write (W) latches as needed.

Once child is locked, check if it is safe:

→ If child is safe, release all locks on ancestors.

18

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SLIDE 44 CMU 15-721 (Spring 2019)

EXAM PLE # 1: SEARCH 23

19

A B D G

20 10 35 6 12 23 38 44

C E F

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SLIDE 45 CMU 15-721 (Spring 2019)

EXAM PLE # 1: SEARCH 23

19

A B D G

20 10 35 6 12 23 38 44

C E F R

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SLIDE 46 CMU 15-721 (Spring 2019)

EXAM PLE # 1: SEARCH 23

19

A B D G

20 10 35 6 12 23 38 44

C E F R R

We can release the latch on A as soon as we acquire the latch for C.

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SLIDE 47 CMU 15-721 (Spring 2019)

EXAM PLE # 1: SEARCH 23

19

A B D G

20 10 35 6 12 23 38 44

C E F R

We can release the latch on A as soon as we acquire the latch for C.

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SLIDE 48 CMU 15-721 (Spring 2019)

EXAM PLE # 1: SEARCH 23

19

A B D G

20 10 35 6 12 23 38 44

C E F R R

We can release the latch on A as soon as we acquire the latch for C.

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SLIDE 49 CMU 15-721 (Spring 2019)

EXAM PLE # 1: SEARCH 23

19

A B D G

20 10 35 6 12 23 38 44

C E F R

We can release the latch on A as soon as we acquire the latch for C.

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SLIDE 50 CMU 15-721 (Spring 2019)

EXAM PLE # 2: DELETE 4 4

20

A B D G

20 10 35 6 12 23 38 44

C E F

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SLIDE 51 CMU 15-721 (Spring 2019)

EXAM PLE # 2: DELETE 4 4

20

A B D G

20 10 35 6 12 23 38 44

C E F W

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SLIDE 52 CMU 15-721 (Spring 2019)

EXAM PLE # 2: DELETE 4 4

20

A B D G

20 10 35 6 12 23 38 44

C E F W W

We may need to coalesce C, so we can’t release the latch on A.

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SLIDE 53 CMU 15-721 (Spring 2019)

EXAM PLE # 2: DELETE 4 4

20

A B D G

20 10 35 6 12 23 38 44

C E F W W W

We may need to coalesce C, so we can’t release the latch on A. G will not merge with F, so we can release latches on A and C.

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SLIDE 54 CMU 15-721 (Spring 2019)

EXAM PLE # 2: DELETE 4 4

20

A B D G

20 10 35 6 12 23 38 44

C E F W

We may need to coalesce C, so we can’t release the latch on A. G will not merge with F, so we can release latches on A and C.

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SLIDE 55 CMU 15-721 (Spring 2019)

EXAM PLE # 2: DELETE 4 4

20

A B D G

20 10 35 6 12 23 38 44

C E F W

We may need to coalesce C, so we can’t release the latch on A. G will not merge with F, so we can release latches on A and C.

X

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SLIDE 56 CMU 15-721 (Spring 2019)

EXAM PLE # 3: IN SERT 4 0

21

A B D G

20 10 35 6 12 23 38 44

C E F

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SLIDE 57 CMU 15-721 (Spring 2019)

EXAM PLE # 3: IN SERT 4 0

21

A B D G

20 10 35 6 12 23 38 44

C E F W

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SLIDE 58 CMU 15-721 (Spring 2019)

EXAM PLE # 3: IN SERT 4 0

21

A B D G

20 10 35 6 12 23 38 44

C E F W W

C has room if its child has to split, so we can release the latch on A.

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SLIDE 59 CMU 15-721 (Spring 2019)

EXAM PLE # 3: IN SERT 4 0

21

A B D G

20 10 35 6 12 23 38 44

C E F W

C has room if its child has to split, so we can release the latch on A.

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SLIDE 60 CMU 15-721 (Spring 2019)

EXAM PLE # 3: IN SERT 4 0

21

A B D G

20 10 35 6 12 23 38 44

C E F W W

C has room if its child has to split, so we can release the latch on A. G has to split, so we can’t release the latch on C.

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SLIDE 61 CMU 15-721 (Spring 2019)

EXAM PLE # 3: IN SERT 4 0

21

A B D G

20 10 35 6 12 23 38 44

C E F W W

C has room if its child has to split, so we can release the latch on A. G has to split, so we can’t release the latch on C.

H

44

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SLIDE 62 CMU 15-721 (Spring 2019)

EXAM PLE # 3: IN SERT 4 0

21

A B D G

20 10 35 6 12 23 38 44

C E F W W

C has room if its child has to split, so we can release the latch on A. G has to split, so we can’t release the latch on C.

H

44 40 44

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SLIDE 63 CMU 15-721 (Spring 2019)

EXAM PLE # 3: IN SERT 4 0

21

A B D G

20 10 35 6 12 23 38 44

C E F

C has room if its child has to split, so we can release the latch on A. G has to split, so we can’t release the latch on C.

H

44 40 44

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SLIDE 64 CMU 15-721 (Spring 2019)

O BSERVATIO N

What was the first step that the DBMS took in the two examples that updated the index?

22

Delete 44

A

20

W

Insert 40

A

20

W

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SLIDE 65 CMU 15-721 (Spring 2019)

BETTER LATCH CRABBIN G

Optimistically assume that the leaf is safe.

→ Take R latches as you traverse the tree to reach it and verify. → If leaf is not safe, then do previous algorithm.

23

CONCURRENCY O OF OPERATIONS ON B- TREES

ACTA I INFORMATICA 1977

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SLIDE 66 CMU 15-721 (Spring 2019)

EXAM PLE # 4 : DELETE 4 4

24

A B D G

20 10 35 6 12 23 38 44

C E F

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SLIDE 67 CMU 15-721 (Spring 2019)

EXAM PLE # 4 : DELETE 4 4

24

A B D G

20 10 35 6 12 23 38 44

C E F R

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SLIDE 68 CMU 15-721 (Spring 2019)

EXAM PLE # 4 : DELETE 4 4

24

A B D G

20 10 35 6 12 23 38 44

C E F R R

We assume that C is safe, so we can release the latch on A.

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SLIDE 69 CMU 15-721 (Spring 2019)

EXAM PLE # 4 : DELETE 4 4

24

A B D G

20 10 35 6 12 23 38 44

C E F R

We assume that C is safe, so we can release the latch on A.

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SLIDE 70 CMU 15-721 (Spring 2019)

EXAM PLE # 4 : DELETE 4 4

24

A B D G

20 10 35 6 12 23 38 44

C E F R

We assume that C is safe, so we can release the latch on A. Acquire an exclusive latch on G.

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SLIDE 71 CMU 15-721 (Spring 2019)

EXAM PLE # 4 : DELETE 4 4

24

A B D G

20 10 35 6 12 23 38 44

C E F W

We assume that C is safe, so we can release the latch on A. Acquire an exclusive latch on G.

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SLIDE 72 CMU 15-721 (Spring 2019)

EXAM PLE # 4 : DELETE 4 4

24

A B D G

20 10 35 6 12 23 38 44

C E F W

We assume that C is safe, so we can release the latch on A. Acquire an exclusive latch on G.

X

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SLIDE 73 CMU 15-721 (Spring 2019)

O BSERVATIO N

Crabbing ensures that txns do not corrupt the internal data structure during modifications. But because txns release latches on each node as soon as they are finished their operations, we cannot guarantee that phantoms do not occur…

25

slide-74
SLIDE 74 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

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SLIDE 75 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1:

R

READ(25)

slide-76
SLIDE 76 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1:

R R

READ(25)

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SLIDE 77 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1:

R

READ(25)

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SLIDE 78 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1:

R

!

READ(25)

slide-79
SLIDE 79 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1: Txn #2:

INSERT(25) READ(25)

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SLIDE 80 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1: Txn #2:

W

INSERT(25) READ(25)

slide-81
SLIDE 81 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1: Txn #2:

25

W

INSERT(25) READ(25)

slide-82
SLIDE 82 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1: Txn #2: Txn #1:

25

INSERT(25) READ(25) INSERT(25)

slide-83
SLIDE 83 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 1

26

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1: Txn #2: Txn #1:

25

W

INSERT(25) READ(25) INSERT(25)

slide-84
SLIDE 84 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 2

27

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1:

[12,23]

slide-85
SLIDE 85 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 2

27

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1:

R

[12,23]

slide-86
SLIDE 86 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 2

27

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1:

R R

[12,23]

slide-87
SLIDE 87 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 2

27

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1: Txn #2:

W W

INSERT(21) [12,23]

slide-88
SLIDE 88 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 2

27

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1: Txn #2:

23 21

W W

INSERT(21) [12,23]

slide-89
SLIDE 89 CMU 15-721 (Spring 2019)

PRO BLEM SCEN ARIO # 2

27

A B D G

20 10 35 6 12 23 38 44

C E F

Txn #1: Txn #2:

23 21

Txn #1:

R R

INSERT(21) [12,23] [12,23]

slide-90
SLIDE 90 CMU 15-721 (Spring 2019)

IN DEX LO CKS

Need a way to protect the index’s logical contents from other txns to avoid phantoms. Difference with index latches:

→ Locks are held for the entire duration of a txn. → Only acquired at the leaf nodes. → Not physically stored in index data structure.

Can be used with any order-preserving index.

28

slide-91
SLIDE 91 CMU 15-721 (Spring 2019)

IN DEX LO CKS

29

Lock Table

txn1

X

txn2

S

txn3

S

  • • •

txn3

S

txn2

S

txn4

S

  • • •

txn4

IX

txn6

X

txn5

S

  • • •
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SLIDE 92 CMU 15-721 (Spring 2019)

IN DEX LO CKIN G SCH EM ES

Predicate Locks Key-Value Locks Gap Locks Key-Range Locks Hierarchical Locking

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SLIDE 93 CMU 15-721 (Spring 2019)

PREDICATE LO CKS

Proposed locking scheme from System R.

→ Shared lock on the predicate in a WHERE clause of a SELECT query. → Exclusive lock on the predicate in a WHERE clause of any UPDATE, INSERT, or DELETE query.

Never implemented in any system.

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THE NOTIONS OF CONSISTENCY AND PREDICATE LOCKS IN A DATABASE SYSTEM

CACM 1976

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SLIDE 94 CMU 15-721 (Spring 2019)

PREDICATE LO CKS

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SELECT SUM(balance) FROM account WHERE name = 'Biggie' INSERT INTO account (name, balance) VALUES ('Biggie', 100);

name='Biggie' name='Biggie'∧ balance=100 Records in Table "account"

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SLIDE 95 CMU 15-721 (Spring 2019)

KEY- VALUE LO CKS

Locks that cover a single key value. Need “virtual keys” for non-existent values.

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10 12 14 16

B+Tree Leaf Node

Key [14, 14]

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SLIDE 96 CMU 15-721 (Spring 2019)

GAP LO CKS

Each txn acquires a key-value lock on the single key that it wants to access. Then get a gap lock on the next key gap.

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10 12 14 16

{Gap} {Gap} {Gap}

B+Tree Leaf Node

Gap (14, 16)

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SLIDE 97 CMU 15-721 (Spring 2019)

KEY- RAN GE LO CKS

A txn takes locks on ranges in the key space.

→ Each range is from one key that appears in the relation, to the next that appears. → Define lock modes so conflict table will capture commutativity of the operations available.

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SLIDE 98 CMU 15-721 (Spring 2019)

KEY- RAN GE LO CKS

Locks that cover a key value and the gap to the next key value in a single index.

→ Need “virtual keys” for artificial values (infinity)

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10 12 14 16

{Gap} {Gap} {Gap}

B+Tree Leaf Node

Next Key [14, 16)

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SLIDE 99 CMU 15-721 (Spring 2019)

KEY- RAN GE LO CKS

Locks that cover a key value and the gap to the next key value in a single index.

→ Need “virtual keys” for artificial values (infinity)

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10 12 14 16

{Gap} {Gap} {Gap}

B+Tree Leaf Node

Prior Key (12, 14]

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SLIDE 100 CMU 15-721 (Spring 2019)

H IERARCH ICAL LO CKIN G

Allow for a txn to hold wider key-range locks with different locking modes.

→ Reduces the number of visits to lock manager.

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10 12 14 16

{Gap} {Gap} {Gap}

B+Tree Leaf Node

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SLIDE 101 CMU 15-721 (Spring 2019)

H IERARCH ICAL LO CKIN G

Allow for a txn to hold wider key-range locks with different locking modes.

→ Reduces the number of visits to lock manager.

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10 12 14 16

{Gap} {Gap} {Gap}

B+Tree Leaf Node

IX

[10, 16)

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SLIDE 102 CMU 15-721 (Spring 2019)

H IERARCH ICAL LO CKIN G

Allow for a txn to hold wider key-range locks with different locking modes.

→ Reduces the number of visits to lock manager.

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10 12 14 16

{Gap} {Gap} {Gap}

B+Tree Leaf Node

IX

[10, 16) [14, 16)

X

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SLIDE 103 CMU 15-721 (Spring 2019)

H IERARCH ICAL LO CKIN G

Allow for a txn to hold wider key-range locks with different locking modes.

→ Reduces the number of visits to lock manager.

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10 12 14 16

{Gap} {Gap} {Gap}

B+Tree Leaf Node

IX

[10, 16) [14, 16)

X IX

[12, 12]

X

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SLIDE 104 CMU 15-721 (Spring 2019)

PARTIN G TH O UGH TS

Hierarchical locking essentially provides predicate locking without complications.

→ Index locking occurs only in the leaf nodes. → Latching is to ensure consistent data structure.

Peloton currently does not support serializable isolation with range scans.

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SLIDE 105 CMU 15-721 (Spring 2019)

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ANDY’S

TIPS FOR PROFILING

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SLIDE 106 CMU 15-721 (Spring 2019)

M OTIVATIO N

Consider a program with functions foo and bar. How can we speed it up with only a debugger ?

→ Randomly pause it during execution → Collect the function call stack

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SLIDE 107 CMU 15-721 (Spring 2019)

RAN DO M PAUSE M ETH O D

Consider this scenario

→ Collected 10 call stack samples → Say 6 out of the 10 samples were in foo

What percentage of time was spent in foo?

→ Roughly 60% of the time was spent in foo → Accuracy increases with # of samples

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SLIDE 108 CMU 15-721 (Spring 2019)

Say we optimized foo to run two times faster What’s the expected overall speedup ?

→ 60% of time spent in foo drops in half → 40% of time spent in bar unaffected

By Amdahl’s law, overall speedup =

1

𝒒 𝒕+(1−𝒒)

→ p = percentage of time spent in optimized task → s = speed up for the optimized task → Overall speedup =

1

0.6 2 +0.4 = 1.4 times faster 108

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SLIDE 109 CMU 15-721 (Spring 2019)

PRO FILIN G TO O LS FO R REAL

Choice #1: Valgrind

→ Heavyweight binary instrumentation framework with different tools to measure different events.

Choice #2: Perf

→ Lightweight tool that uses hardware counters to capture events during execution.

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SLIDE 110 CMU 15-721 (Spring 2019)

CH O ICE # 1: VALGRIN D

Instrumentation framework for building dynamic analysis tools.

→ memcheck: a memory error detector → callgrind: a call-graph generating profiler → massif: memory usage tracking.

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SLIDE 111 CMU 15-721 (Spring 2019)

Using callgrind to profile the index test and Peloton in general: Profile data visualization tool:

$ kcachegrind callgrind.out.12345

KCACH EGRIN D

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$ valgrind --tool=callgrind --trace-children=yes ./relwithdebinfo/concurrent_read_benchmark

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SLIDE 112 CMU 15-721 (Spring 2019)

Using callgrind to profile the index test and Peloton in general: Profile data visualization tool:

$ kcachegrind callgrind.out.12345

KCACH EGRIN D

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$ valgrind --tool=callgrind --trace-children=yes ./relwithdebinfo/concurrent_read_benchmark

Cumulative Time Distribution Callgraph View

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SLIDE 113 CMU 15-721 (Spring 2019)

CH O ICE # 2: PERF

Tool for using the performance counters subsystem in Linux.

→ -e = sample the event cycles at the user level only → -c = collect a sample every 2000 occurrences of event

Uses counters for tracking events

→ On counter overflow, the kernel records a sample → Sample contains info about program execution

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$ perf record -e cycles:u -c 2000 ./relwithdebinfo/concurrent_read_benchmark

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SLIDE 114 CMU 15-721 (Spring 2019)

PERF VISUALIZATIO N

We can also use perf to visualize the generated profile for our application. There are also third-party visualization tools:

→ Hotspot

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$ perf report

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SLIDE 115 CMU 15-721 (Spring 2019)

PERF VISUALIZATIO N

We can also use perf to visualize the generated profile for our application. There are also third-party visualization tools:

→ Hotspot

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$ perf report

Cumulative Event Distribution

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SLIDE 116 CMU 15-721 (Spring 2019)

PERF VISUALIZATIO N

We can also use perf to visualize the generated profile for our application. There are also third-party visualization tools:

→ Hotspot

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$ perf report

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SLIDE 117 CMU 15-721 (Spring 2019)

PERF VISUALIZATIO N

We can also use perf to visualize the generated profile for our application. There are also third-party visualization tools:

→ Hotspot

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$ perf report

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SLIDE 118 CMU 15-721 (Spring 2019)

PERF VISUALIZATIO N

We can also use perf to visualize the generated profile for our application. There are also third-party visualization tools:

→ Hotspot

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$ perf report

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SLIDE 119 CMU 15-721 (Spring 2019)

PERF EVEN TS

Supports several other events like:

→ L1-dcache-load-misses → branch-misses

To see a list of events: Another usage example:

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$ perf list $ perf record -e cycles,LLC-load-misses -c 2000 ./relwithdebinfo/concurrent_read_benchmark

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SLIDE 120 CMU 15-721 (Spring 2019)

REFEREN CES

Valgrind

→ The Valgrind Quick Start Guide → Callgrind → Kcachegrind → Tips for the Profiling/Optimization process

Perf

→ Perf Tutorial → Perf Examples → Perf Analysis Tools

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SLIDE 121 CMU 15-721 (Spring 2019)

N EXT CLASS

Index Key Representation Memory Allocation & Garbage Collection T-Trees (1980s / TimesTen) Bw-Tree (Hekaton) Concurrent Skip Lists (MemSQL)

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