Adding a New Dimension to Physical Design Sachin Sapatnekar - PowerPoint PPT Presentation

Adding a New Dimension to Physical Design Sachin Sapatnekar University of Minnesota 1

Outline • What is 3D about? • Why 3D? • 3D-specific challenges • 3D analysis and optimization 2

Planning a city: Land usage [Somewhere in the American midwest; pop. density typically about 20 persons/km 2 ] [New York= 10,600/km 2 ] [Minneapolis, p.d. = 2,700/km 2 ] [SF= 6,688/km 2 ] 3

Types of 3D circuits PCB stacking Memory – vertical TFTs Wafer stacking [www.irvine-sensors.com] [Matrix Semiconductor] [Fraunhofer IZM] Example application Back- - Back Metal Metal Antenna Layer Antenna Layer Isolation Isolation plane plane LNA / Mixer LNA / Mixer Down- Down - conversion conversion layer: layer: IF, IF, ADC, ADC, Digital Digital Baseband Baseband Digital Digital processing processing 4

Example of a commercial application 5 [Beyne, IMEC]

Example 3D processes [H. Hedler, ISSCC 2007 Qimonda] [Koyanagi, Tohoku U./Zycube] [Hedler, Qimonda] [IBM] 6 6

Through-silicon vias (TSVs) Keep-out distance [Tezzarron] [Nowak, Qualcomm] 7

Schematic of a 3D IC Detailed view Generalized view Interlayer Via Layer 5 SOI wafers with bulk Layer 4 substrate removed Inter-layer Layer 3 bonds 1 µ m Layer 2 Bulk wafer Metal level ~10 µ m Layer 1 of wafer 1 ~500 µ m Bulk Substrate Device level 1 Adapted from [Das et al., ISVLSI , 2003] by B. Goplen 8

Outline • What is 3D about? • Why 3D? • 3D-specific challenges • 3D analysis and optimization 9

Another “dimension” to scaling [Intel] 3D provides an alternative avenue towards increasing system sizes Orthogonal to device scaling 10

3D Interconnects • Reduced wire lengths 2D DRAM DRAM Thermal Gradient 3D DRAM DRAM • Theoretically DRAM For an L × L 2D chip, max – 2 L wire length reduces from 2 L to L2 Cache m 3D Global Net Distributions CPU & 1400 Net Density (#/mm) L1Cache 1200 4 Strata 2 Strata 1000 1 Stratum 800 600 Heat Sink 400 200 0 0 5 10 15 20 25 30 35 Length (mm) 11

Why are shorter wires good? • Sequential critical length (“cycle reach”) trends 7 6 8x wire Relative 5 critical 4 seq. 3 length 2 1 4x wire M6 0 M3 90nm 65nm 45nm 32nm 2x wire [Intel] P6, ~ core cycle reach [IBM] 1x wire 65nm, ~ 5.2 GHz • Critical interbuffer length also shrinking (i.e., buffer count increasing) 12

Other benefits • Improved isolation in 3D • Heterogeneous integration – Critical for analog/RF ckts – Different layers can be made of different materials – Lower digital/mixed-signal noise – Can integrate, for example • CMOS – Shielding is possible either using metal layers, or by • GaAs leveraging bonding material • Optical elements (VCSELs) • MEMS/NEMS • Exotic cooling technologies (micropumps, piezoelectric [Das et al. , ISPD04] devices, microrefrigerators) (Cu) 13

Outline • What is 3D about? • Why 3D? • 3D-specific challenges • 3D analysis and optimization 14

Geometrical challenges Detailed view Generalized view Interlayer Via Layer 5 SOI wafers with bulk Layer 4 substrate removed Inter-layer Layer 3 bonds 1 µ m Layer 2 Bulk wafer Metal level 10 µ m Layer 1 of wafer 1 500 µ m Bulk Substrate Device level 1 Adapted from [Das et al., ISVLSI , 2003] by B. Goplen 15

Thermal challenges • Each layer generates heat • Heat sink at the end(s) • Simple analysis Layer 5 – Power(3D)/Power(2D) = m • m = # layers Layer 4 – Let R sink = thermal resistance of heat sink – T = Power × R sink Layer 3 • m times worse for 3D! • And this does not account for Layer 2 – Increased effective R sink – Leakage power effects, T-leakage feedback Layer 1 • Thermal bottleneck: a major problem for 3D Bulk Substrate 16

Thermal impact on circuit performance • Gate delays change with T • Wire delays change with T – Mobility goes down • Leakage increases with T • Reliability degrades with T – V th goes down – NBTI, electromigration SiH + h + → Si + + ½H 2 Si H – Which effect wins? Si H H 2 Si H – Positive, negative, mixed T Substrate Gate Oxide Poly dependency • Can use better heat sinks, but… The same circuit at various process corners Heat sink cost vs. Power 17

Power delivery challenges • Each layer draws current from the power grid • Power pins at the extreme end tier(s) • Simple analysis Layer 5 – Current(3D)/Current(2D) = m • m = # layers Layer 4 – Let R grid = resistance of power grid – V drop = Current × R grid • m times worse for 3D! Layer 3 • And this does not account for – Increased effective R grid Layer 2 – Leakage power effects, increased current due to T-leakage feedback Layer 1 • Power bottleneck: a major problem for 3D Bulk Substrate 18

Power supply integrity in 3D • Greater challenge in 3D due to via resistance, limited number of supply pins Current per power pin (2D) – ITRS Pins The Trend of Current per Power Pin from ITRS 300 250 Current per Power Pin (mA) 3D 2D 200 [Zhan, ICCAD07] 150 100 50 0 2005 2010 2015 2020 2025 Year 19

Yield/test challenges • Yield due to spot defects reduces exponentially with area – Smaller areas imply better yield – Stack together smaller die; yield improves! – (Note that stacking wafers together does not help!) [Mak, Intel] • Problem – Need to have known-good die (KGD) – Must test die prior to 3D assembly • Testing thinned die is hard: mechanically too weak for probe pressure! • Can test die prior to thinning – but then, connections to other layers are untested! 20

Outline • What is 3D about? • Why 3D? • 3D-specific challenges • 3D analysis and optimization 21

Thermal analysis • Heat generation – Switching gates/blocks act as heat sources – Time constants for heat of the order of ms or more • Thermal equation: partial differential equation ∂ 2 ∂ 2 ∂ 2 T T T + + + = Q(x, y, z) 0 K K K x y z ∂ ∂ ∂ 2 2 2 x y z • Boundary conditions corresponding to the ambient, heat sink, etc. • Self-consistency – Power = f(T) – T = g(Power) 22

Thermal solution techniques • Numerical: solve large, sparse systems of linear equations – Finite difference method: thermal – electrical equivalence • System structure is similar to power grids (good!) + ~ ... ... heat sources wafer y z ... ... x ambient temperature + ~ – Current sources ↔ power, voltage ↔ temperature – Finite element method • Semi-analytical – Green functions (fast, appropriate for early analysis) 23

Thermal optimization • Minimize power usage P cells R chip • Rearrange heat sources • Improved thermal conduits Chip R heat sink • Improved heat sinking Heat Sink 24

3D floorplanning [Zhou, ICCAD07] 25

3D placement • Incorporate thermal issues IOPad 1 Cell 3 Cell 4 • Force-directed vs. Net1 Net2 partitioning methods Cell 1 IOPad 2 Net3 Cell 5 Cell 2 TRR Net 4 TRR Net 5 TRR Net 1 TRR Net 3 TRR Net 2 Heat Sink 26

Interlayer via count vs. wirelength (ibm01) 9000 2 layers 8000 4 layers 3 layers 5 layers 7000 Interlayer Vias per Interlayer 10 10 layers layers 6000 9 layers 8 layers 5000 7 layers 6 layers 4000 5 layers 4 layers 3000 3 layers 2000 1000 1 layer 0 1 1.5 2 2.5 3 3.5 4 4.5 Wirelength, m 27

Thermal vias Thermal Via Substrate Thermal Via Region Row Region Inter-Row Region • Thermal vias – Electrically isolated vias } Inter-layer – Used for heat conduction } Layer • Thermal via regions } Bulk Substrate – Contains thermal vias – Predictable obstacle for routing – Variable density of thermal vias z y x 28

Temperature profile Before Thermal Via Placement After Thermal Via Placement 29

Thermal via insertion Temperature Profile Thermal Via Regions 30

3D routing with integrated thermal via insertion • Build good heat conduction path through dielectric: • Thermal vias: interlayers vias dedicated to thermal conduction. • Thermal wires: metal wires improves lateral heat conduction. • Thermal vias + thermal wires a thermal conduction network. thermal vias thermal wires • Thermal wires compete with lateral signal wire routing. • Thermal vias: large, can block lateral signal routing capacity. [Zhang, ASPDAC06] 31

Active cooling techniques Polymer cover TWV Si Si microchannel heat sink Si Die “Trimodal I/O” Optical I/O Electrical I/O Fluidic I/O Optical I/O Fluidic I/O [Bakir, GaTech - CICC 07] 32

Microfluidic cooling Si Die TSV-E TSV-F 100 Trimodal Flow rate = 34 ml/min I/Os 90 Flow rate = 78 ml/min Temperature rise on heaters (C) Area: 8 mm 2 Flow rate = 104 ml/min 80 Fluidic Flow rate = 125 ml/min channel 70 Cu wire Optical waveguide 60 50 40 30 20 10 0 0 50 100 150 200 250 300 350 Localized power density (W/cm2) [Bakir, GaTech] 33

3D and multicore systems NoCs 3D bus/NoC hybrid [Karnik, Intel] [Xie, Penn State] 34