A Configurable Hardware Scheduler A Configurable Hardware Scheduler - - PowerPoint PPT Presentation

A Configurable Hardware Scheduler A Configurable Hardware Scheduler (CHS) for Real (CHS) for Real-

• Time Systems

Time Systems

Pramote Kucharoen, Mohamed A. Shalan and Vincent J. Mooney III

Center for Research on Embedded Systems and Technology School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, Georgia, USA

23 June 2003

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Outline Outline

• Introduction
• Related work
• CHS architecture
• CHS commands
• CHS interface
• Software support
• Automatic customization of CHS
• Experiments and results
• Conclusion

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Introduction Introduction

Real-time system layers Application Application RTOS RTOS Hardware Hardware

Task1 Task2 Task3 Application 1 Task1 Task2 Task3 Application 2 Core Time Task Scheduler CHS Support Memory I/O CPU

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µ µ µ µ µ µ µ µC C/OS II Background Processing /OS II Background Processing

ptcb = OSTCBList; /* Point at first TCB in TCB list */ while (ptcb->OSTCBId != OS_TASK_IDLE_ID) { /* Go through all TCBs in TCB list */ OS_ENTER_CRITICAL(); if (ptcb->OSTCBDly != 0) { /* Delayed or waiting for event with TO */ if (--ptcb->OSTCBDly == 0) { /* Decrement nbr of ticks to end of delay */ if (!(ptcb->OSTCBStat & OS_STAT_SUSPEND)) /* Is task suspended? */ OSSched(ptcb,RDY); else /* Yes, Leave 1 tick to prevent loosing */ ptcb->OSTCBDly = 1; /* the task when the suspension is removed. */ } } ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ OS_EXIT_CRITICAL(); }

NOT FIXED-CYCLE OPERATIONS Number of Tasks Dependent

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Overhead in Overhead in µ µ µ µ µ µ µ µC C/OS II Scheduler /OS II Scheduler

0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 10 100 1000 Time tick resolution (usec) Overhead %

64 tasks 32 tasks 4 tasks 8 tasks 16 tasks

Time tick Resolution Dependence

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Related Work Related Work

Inflexible Inflexible Only One Scheduling Discipline Only One Scheduling Discipline

Packet Scheduler Packet Scheduler FASTHARD FASTHARD FASTCHART FASTCHART

Not for Adaptive Systems Not for Adaptive Systems

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Why do we need the CHS? Why do we need the CHS?

• To reduce the scheduling overhead from the real-

time operating system; hence, improve the system response time

• To support a wide range of applications by

supporting multiple scheduling disciplines that can be changed during system execution time.

– Priority – Earliest Dead Line First (EDF) – Rate Monotonic (RM)

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CHS Architecture (1) CHS Architecture (1)

Tasks Table Tasks Table

I nterrupt Controller I nterrupt Controller

. . . . . I nt 0 I nt 1 I nt 7

SQ SQ PQ PQ

Current Task Current Task

Control Unit Control Unit

Control Signals Bus I nterface Signals

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REG + Counter LOGI C Comparator REG + Counter LOGI C Comparator REG + Counter LOGI C Comparator

CHS Architecture (2) CHS Architecture (2)

Priority Queue (Ready Queue)

I D Register Counter

REG + Counter LOGI C Comparator Comparison results from the right block New Data Comparison Results

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CHS Architecture (3) CHS Architecture (3)

Sleep Queue

• Used to store the Sleeping Tasks (YIELD/SLEEP).
• The Tasks are sorted according to their remaining sleep time.
• Once The Sleep Time expires it is moved to the PQ.

I D Counter

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CHS Architecture (4) CHS Architecture (4)

Task Table

• Store Information about the existing tasks
• Indexed by the Task ID

PRI Period WCET TYPE PRE STATUS

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CHS Commands CHS Commands

1 DELETE 1 RESUME 1 SUSPEND 1 YIELD 1 SSLEEP 2 SLEEP 2 MODIFY Task 1 CREATE Task Task Related 1 CONFIGURE 1 RUN 1 STOP Scheduler Related # of Cycles Command

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CHS Interface CHS Interface

The CHS Hardware is designed to be able to interface easily to any microprocessor core:

– As a memory mapped I/O Port, – As a co-processor, or – As instruction-set accelerator

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Software Support Software Support

APIs

• Task

– createTask – suspendTask, resumeTask – changePriority, changeWCET, changePeriod – Yield – ssleep, sleep

• Scheduler

– configureScheduler – enableScheduler, disableScheduler

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Automatic Customization of CHS Automatic Customization of CHS

SCon SCon VPP VPP Customized HW Customized HW HW DB HW DB SW DB SW DB Customized RTOS Customized RTOS DC Synthesis Script DC Synthesis Script

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Experiments and Results (1) Experiments and Results (1)

Simulation Environment

VCS VCS Seamless CVE Seamless CVE XRAY XRAY

Memory Memory MPC750 MPC750 Hardware Scheduler Hardware Scheduler

Address/Data Bus Interrupt

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Experiments and Results (2) Experiments and Results (2)

47+47*(number of tasks) Time-tick processing 69 Scheduler* Hardware Scheduler Micro C/OS II 125 21 SuspendTask 230 37 configureScheduler WCET (# of cycles) # of PPC Assembly Instructions API

Assembly instruction execution comparison Number of PowerPC instruction of the APIs

CHS Requires One PPC Instruction to be Configured and One Instruction to Suspend a Task which means over 100x Speedup.

* Priority Scheduler

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Experiments and Results (3) Experiments and Results (3)

Fixed-Cycle Operations Fixed-Cycle Operations Improve Response Time Improve Response Time Time tick background processing Time tick background processing Scheduling in Software Scheduling in Software

CHS CHS

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CHS Synthesis Results CHS Synthesis Results

The Synthesized CHS Supports

– 16 Tasks and – up to 8 interrupt sources

0.24 1115 Area (mm2) Number of standard cells 564 421 Number of Registers Number of Logic Elements Using HP 0.35µ µ µ µ process Using Altera Quartus II for EP20K

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Conclusion Conclusion

• We implemented a configurable hardware scheduler

that supports 3 scheduling algorithms

• We developed software interface for the configurable

hardware scheduler and a tool to generate a customized synthesizable CHS

• The configurable hardware scheduler eliminated the

time spent by the processor for background time tick processing and scheduling

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Questions? Questions?