Overview of Overview of *configurable* architectures - - PDF document

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Overview of Overview of *configurable* architectures - - PDF document

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Overview of Overview of *configurable* architectures *configurable* architectures Prof. Kurt Keutzer EECS keutzer@eecs.berkeley.edu Thanks to Andre Dehon, Jan Rabaey, and many vendors 1 Outline Outline Motivation for *configurable*

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Overview of Overview of *configurable* architectures *configurable* architectures

  • Prof. Kurt Keutzer

EECS keutzer@eecs.berkeley.edu

Thanks to Andre Dehon, Jan Rabaey, and many vendors

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Outline Outline

  • Motivation for *configurable* platforms
  • Taxonomy of *configurable* platforms
  • Examples of *configurable* platforms
  • Projects in *configurable* platforms
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Increasing Device and Context Complexity Increasing Device and Context Complexity

  • Exponential increase in device complexity—increasing

with Moore’s law (or faster)!

  • System context in which devices are deployed (e.g.

cellular radio) are increasing in complexity as well exponential increases in design productivity

Complexity

We have exponentially more transistors!

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Deep Submicron Effects Deep Submicron Effects

  • Smaller geometries are causing a wide variety of effects that we

have largely ignored in the past: – Cross-coupled capacitances – Signal integrity – Resistance – Inductance

DSM Effects

Design of each transistor is getting more difficult!

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Heterogeneity on Chip Heterogeneity on Chip

  • Greater diversity of on-chip elements

– Processors – Software – Memory – Analog

More transistors doing different things!

Heterogeneity

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Stronger Market Pressures Stronger Market Pressures

  • Decreasing design window
  • Less tolerance for design revisions

Exponentially more complex, greater design risk, greater variety, and a smaller design window ! Time-to-Money

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Motivation: Quadruple Motivation: Quadruple-

  • Whammy

Whammy

DSM Effects Complexity Heterogeneity Time-to-Money

Exponentially more complex, greater design risk, greater variety, and a smaller design window !

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Likely alternative… Likely alternative…

  • Unprecedented hunger for silicon customization

but ...

  • The quadruple-whammy implies:

– Higher NRE/design – Growing number of applications served through more highly-programmable platforms – With higher-design volume to compensate for higher NREs – From ASIC to ASIP

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Key Problems in IC Design and Their Solution Key Problems in IC Design and Their Solution

Problem:

  • High development (NRE) cost
  • Need to use IC’s for multiple

related applications

  • Minimize design risk/increase

time-to-market Solution:

  • Amortize cost over many

designs by developing platforms

  • Make platform programmable

so that it can be re-used

  • Use pre-developed platform

where possible and tailor it to application through programming

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System ASIC Design in 200x System ASIC Design in 200x

  • Less like synthesis of an

integrated circuit from a high- level description

  • More like programming of a

complex application-specific processor

RTL Synthesis HDL netlist logic

  • ptimization

netlist Library physical design layout Impact Front-End Simulator / Visualization Liberty Back-End MESCAL Liberty MDES MESCAL MDES

Prog Env

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Outline Outline

  • Motivation for *configurable* platforms
  • Taxonomy of *configurable* platforms
  • Projects in *configurable* platforms
  • Examples of *configurable* platforms

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A 3D Design Space A 3D Design Space

Computation Abstraction Level

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Programming Model Programming Model

  • The computation-abstraction level (name designed

by committee) is about how is the level of configurability presented to the user

  • Natural levels:

– System architecture – e.g. hash engine – Instruction-set architecture - e.g. MAC x,y,z – Micro-architecture – operator-level – Logic level – moving bits We’ll find systems offering configurabilty at all these levels

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Design Space: Vertical Axis Design Space: Vertical Axis

Computation Abstraction Level Process/System Architecture Instruction-Set Architecture Micro- Architecture Logic level mov r5, r2

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A 3D Design Space A 3D Design Space

Computation Abstraction Level Reconfigurable Feature

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Reconfigurable Features Reconfigurable Features

  • The reconfigurable-feature (another name designed by

committee) is about the manner in which the device supports the configurability

  • Computation:

– Processes – e.g. processing element – Datapaths - e.g. filtering elements – Operators – adders, multipliers, – Logic level – Look-up tables

  • Communication:

– Bus, mesh, hierarchical mesh, on-chip packet routing

  • We’ll find systems using configurabilty at all these

levels … but

  • Not as straightforward as it seems – processes may be

supported on a logic level fabric

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The Choice of the Computational Elements The Choice of the Computational Elements

Reconfigurable Reconfigurable Logic Logic Reconfigurable Reconfigurable Datapaths Datapaths

adder buffer reg0 reg1 mux

CLB CLB CLB CLB

Data Memory Instruction Decoder & Controller Data Memory Program Memory Datapath MAC In AddrGen Memory AddrGen Memory

Reconfigurable Reconfigurable Arithmetic Arithmetic Reconfigurable Reconfigurable Processors Processors

Bit-Level Operations e.g. encoding

Dedicated data paths e.g. MAC Arithmetic kernels e.g. Convolution, Hash decoding engine Processing elements

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The Choice of the Communication Fabric The Choice of the Communication Fabric

N Inputs B Buses M Outputs

Multi-Bus

cluster cluster cluster

Hierarchical Mesh Mesh

Module

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A 3D Design Space A 3D Design Space

Computation Abstraction Level Reconfigurable Feature Binding Rate

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Binding Rate Binding Rate

  • The binding-rate is about how is the device supports the configurability
  • ver time
  • ``Configurable’’:

– Binding occurs at fabrication time – Similar to ASIC except that the model used to create the devices and the model used to program them is much different » ARC, Tensilica, Improv, Actel

  • ``Re-configurable’’:

– Binding occurs in field, but typically only at ``power-up’’ – Xilinx, Altera, Triscend

  • ``Dynamically reconfigurable’’

– Binding occurs in field, and may occur every 1000’s of cycles – Principally explored in academia – GARP, but also Chameleon

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So you want to be a reconfigurable architect … So you want to be a reconfigurable architect …

  • Think about the applications that you want to

support: – WCDMA, UMTS, packet forwarding, etc.

  • Think about the programming model you want to

provide: – Ptolemy/Models-of-computation, MATLAB, Click, C, assembler, assembly + Verilog

  • Think about the micro-architecture of your device

and the role that reconfigurable fabric plays in it – 80% PE’s and 20% reconfigurable …

  • Do you want to provide configurability,

reconfigurability, dynamic reconfigurability …

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Don’t Forget to Think About This Don’t Forget to Think About This

Flexibility Performance Power Cost

  • Components of Cost

– Area of die / yield – Code density (memory is the major part of die size) – Packaging – Design effort – Programming cost – Time-to-market – Reusability

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Outline Outline

  • Motivation for *configurable* platforms
  • Taxonomy of *configurable* platforms
  • Projects in *configurable* platforms
  • Examples of *configurable* platforms

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*configurable* related 252 Project Ideas *configurable* related 252 Project Ideas - 1

  • Processor/reconfigurable-fabric interface

– utility of a tight link between a processor and reconfigurable fabric depends largely on management of time to: » Reconfigure fabric » Communication overhead – Problem can be addressed by: » Tricks in fabric (caching configurations etc.) » Or … how about learning to fill configuration time much as we learn to fill delay slots in a branch …

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*configurable* related 252 Project Ideas *configurable* related 252 Project Ideas - 2

  • What’s the right fabric?

– Chameleon uses a coarse granularity datapath

  • riented fabric

– Triscend uses a fine-grained fabric – What’s right for your favorite application ….?

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*configurable* related 252 Project Ideas *configurable* related 252 Project Ideas - 3

  • Programming model

– Ultimate success or failure of all these gadgets depends on developing of a programming model for these devices – Develop banana curve for one application for a device that has C-language support try: » Assembly programming the application » C-coding the application » Click, Matlab (details provided), Teja to the device » Compare results – how much do we give up for higher-level programmability –

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Outline Outline

  • Motivation for *configurable* platforms
  • Taxonomy of *configurable* platforms
  • Projects in *configurable* platforms
  • Examples of *configurable* platforms

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Variety of Platforms Variety of Platforms

FPGA Processor

Specialized Micro-Architectures Specialized Instruction-Set Architectures

Domain-Specialization

Chameleon Systems Morphics Frontier Design Tensilica ARC Improv Systems PMC Sierra Xilinx Altera Atmel Triscend Actel Adaptive Silicon Proceler Network Processors

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Here’s the Deal … We can Talk about any of: Here’s the Deal … We can Talk about any of:

  • Actel
  • Adaptive silicon
  • Altera
  • Xilinx
  • Chameleon
  • Morphics
  • Network processors – takes

a whole lecture

  • ARC
  • Improv Systems
  • Tensilica