8051 Serial Port and Timer/Counter Serial Port Timer Counter - - PowerPoint PPT Presentation

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May 10, 2023 188 likes •275 views

8051 Serial Port and Timer/Counter Serial Port Timer Counter Chatchai Jantaraprim (cj@coe.psu.ac.th) 8051 Timer/Counter Two internal Timers/Counters 16-bit timer/counter Timer uses system clock as source of input pulses Counter uses external

SLIDE 1

8051 Serial Port and Timer/Counter

Serial Port Timer Counter

Chatchai Jantaraprim (cj@coe.psu.ac.th)

SLIDE 2

8051 Timer/Counter

Two internal Timers/Counters 16-bit timer/counter Timer uses system clock as source of input pulses Counter uses external input pulses from port 3 (T0,T1) If associated interrupt is enabled, when count overflow an interrupt is generated Registers TH0, TL0 : timer/counter register of timer 0 TH1, TL1 : timer/counter register of timer 1 TMOD : Mode Select register TCON : Control Register

SLIDE 3

8051 Timer/Counter

Timer/Counter Operations Input Source Operation Control Update Mode Input Source 1/12 of Oscillator frequency Pulses received at T0 (P3.4) or T1 (P3.5) Operation Control Pulse is received if conditions (GATEx# or INTx#) and TRx is true

SLIDE 4

8051 Timer/Counter

TMOD and TCON Registers

7 6 5 4 3 1 2 Timer/Counter 0 Timer/Counter 1 C/T# M1 M0 GATE# C/T# M1 M0 GATE# TMOD TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

SLIDE 5

8051 Timer/Counter

TMOD Register M0 and M1Mode Select

Mode 013-bit counter (8192 input pulses) Mode 116-bit counter (65536 input pulses) Mode 28-bit reload Mode 3Two separate 8-bit timer

C/T#Counter/Timer Select

When set, operates as counter input pulse receive from T0/T1 When clear, operates as timer, count increment every 12th system clock pulse

GATE#Gate

if TR0 is set, clearing GATE# enable timer/counter But GATE# is not the only one that can enable timer/counter, if TR0 is set, INT# is also can enable timer/counter

SLIDE 6

8051 Timer/Counter

TCON Register IT0Interrupt 0 Type

When set, falling edge of INT0# cause interrupt When clear, cause interrupt when signal is low, if external signal stays low interrupt will be generated over and over Software control

IE0Interrupt 0 Edge Flag

Set by hardware when external interrupt edge is detected Clear when RETI is executed

IT1Interrupt 1 Type IE1Interrupt 1 Edge Flag

SLIDE 7

8051 Timer/Counter

TCON Register (cont.) TR0Timer 0 Run Control bit

When clear, timer/counter 0 is disable When set, timer/counter 0 is enable (if GATE0# or INT0#) is enable Software control

TF0Timer 0 Overflow Flag

Set by hardware when timer/counter 0 overflows Clear by hardware when processor branches to ISR

TR1Timer 1 Run Control bit TF1Timer 1 Overflow Flag

SLIDE 8

8051 Timer/Counter

Operation Modes Mode 0

13-bit counter, an interrupt is generated when counter overflows It takes 8192 input pulses to generate the next interrupt Mode 1 16-bit counter, similar to mode 0, but take 65536 input pulses Mode 2 8-bit reload TLi operates as timer/counter THi store a number and reload to TLi when overflows Mode 3 Timer 1 is inactive, hold count value TL0 and TH0 operate as two separate 8-bit timer/counter TL0 control by timer 0 control bits TH0 operate as timer driven by system clock, prescaled by 12 and cause timer 1 interrupt overflows